RISC-V: CSR instruction disassembly: Decode CSR register number into a string when a standardized register is used

[pdietl]

Currently, CSR instructions are decoded like so:

But there are many CSR register numbers with a defined definition in the RISC-V ISA Manual Volume II: Privileged Architecture. Examples:

I propose instead of the disassembly showing csrrs zero, 0x300, t0, it instead show csrrs zero, mstatus, t0. Likewise in the higher-level ILs.

I can make these changes, but I'm not great at Rust and I need some pointers on how to do it. Providing an example of the aforementioned instruction would suffice and I could then fill in the rest.

Based on recent contributors, I will humbly ask @emesare, @ehntoo for assistance.

[emesare]

Firstly you want to update the intrinsic param type for csr to an enumeration with the csr register names and their number.

binaryninja-api/arch/riscv/src/lib.rs

Line 540 in 5a5426d

NameAndType::new("csr", Conf::new(Type::int(4, false), MAX_CONFIDENCE)),

You can create an enumeration using EnumerationBuilder:

https://dev-rust.binary.ninja/binaryninja/types/struct.Enumeration.html#method.builder

Then finalizing the enumeration builder and passing it to Type::enumeration:

https://dev-rust.binary.ninja/binaryninja/types/struct.Type.html#method.enumeration

Then you want to update the instruction_text function to special case for those instructions with a csr register numeric.

binaryninja-api/arch/riscv/src/lib.rs

Line 981 in 5a5426d

for (i, oper) in operands.iter().enumerate() {

[pdietl]

@emesare Thanks so much! I'll get on it.