yosys -sim hangs on multiple writes to the same memory address

[aiju]

When simulating a design that contains a multi-port memory, yosys -sim will hang when multiple writes to the same address have different data. It seems to get stuck in update_ph2() because both writes will set the "done_something" flag to true when they see that they changed the memory contents.

I've attached an example case for easier reproduction, including the failing RTLIL rtlil.il (which contains just a single dual-port memory cell), an example input vcd file and a yosys script that shows the issue. Running the script you should see yosys getting stuck in an infinite loop when simulating sample 37.

yosys_bug.zip