You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Please download a minimal reproducible example here:bugmem.tar.gz
The design mem_main.v is just a simple memory interface. We have a memory library memlib.txt which we want to use in synthesis. Running the following script in yosys:
read_verilog mem_main.v
# read_verilog -lib memlib_blackbox.v # this does not matter
hierarchy -check -top main
proc;;
opt_expr; opt_dff; opt_clean
memory -nomap
check # this should be fine
memory_libmap -lib memlib.txt
# techmap -map memlib_blackbox.v # this does not matter
check # this reports problems
Expected Behavior
I expect memory_libmap should not introduce undriven pins.
Actual Behavior
yosys> check
8. Executing CHECK pass (checking for obvious problems).
Checking module main...
Found and reported 0 problems.
yosys> memory_libmap -lib memlib.txt
9. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory main.mem via $__RAM_SYNC_
<suppressed ~52 debug messages>
yosys> check
10. Executing CHECK pass (checking for obvious problems).
Checking module main...
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$98 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$97 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$96 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$95 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$94 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$93 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$92 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$91 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$90 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$89 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$88 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$87 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$86 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$85 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$84 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$83 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$82 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$81 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$80 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$79 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$78 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$77 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$76 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$75 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$74 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$73 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$72 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$71 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$70 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$69 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$68 [0] is used but has no driver.
Warning: Wire main.$auto$memory_libmap.cc:1950:emit_port$67 [0] is used but has no driver.
Found and reported 32 problems.
The pins generated by memory_libmap are undriven.
I thought this was because I didn't give yosys the memory module blackbox definition. However, I've tried read_verilog -lib and techmap -map and still see the same problem.
Another problem that might be related: if I subsequently run
synth -flatten
write_verilog main.gv
I found 32 memory blocks are used but actually 1 should be sufficient.
The text was updated successfully, but these errors were encountered:
I found 32 memory blocks are used but actually 1 should be sufficient.
I have noticed that too, it's due to memory_libmap not making the inference that all the bits of the word share the write enable signal. Maybe the recommended memory inference script isn't enough.
Version
Yosys 0.43+11 (git sha1 49f5477, g++ 9.4.0-1ubuntu1~20.04.2 -fPIC -Os)
On which OS did this happen?
Linux
Reproduction Steps
Please download a minimal reproducible example here: bugmem.tar.gz
The design
mem_main.v
is just a simple memory interface. We have a memory librarymemlib.txt
which we want to use in synthesis. Running the following script in yosys:Expected Behavior
I expect
memory_libmap
should not introduce undriven pins.Actual Behavior
The pins generated by
memory_libmap
are undriven.I thought this was because I didn't give yosys the memory module blackbox definition. However, I've tried
read_verilog -lib
andtechmap -map
and still see the same problem.Another problem that might be related: if I subsequently run
I found 32 memory blocks are used but actually 1 should be sufficient.
The text was updated successfully, but these errors were encountered: