"reg" values of typedeffed types

[sassanp]

Feature Description

The following is a minimal example of what is not working:
`
typedef struct packed {
bit bit1;
} testtype_t;

module testmod;
wire testtype_t testwire; // fine
reg testtype_t testreg; // bad
endmodule
`

With 'iverilog -g2012 test.sv' it works fine.

With '/opt/oss-cad-suite/bin/yosys -p "read_verilog -sv test.sv"' it fails with the following error:
test.sv:7: ERROR: syntax error, unexpected TOK_USER_TYPE

Yosys 0.44+60 (git sha1 0fc5812, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

[zachjs]

This example is not accepted by any other tools I have tested. I think iverilog's behavior here is non-standard.

Relevant portion of the grammar in IEEE 1800-2017 Section 6.8 suggest that a type_identifier cannot follow reg.

data_type ::=
    integer_vector_type [ signing ] { packed_dimension }
    ...
integer_vector_type ::= bit | logic | reg