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stc.h
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#ifndef __STC15_H_
#define __STC15_H_
/////////////////////////////////////////////////
// Original header file generated by STC-ISP.
// Language translation, conversion from Keil C51
// to SDCC and expanded comments by Ashlyn Black, 20/Aug/2020.
/////////////////////////////////////////////////
/////////////////////////////////////////////////
// Note: For STC15W4K32S4 series chips, all IO ports related to PWM are
// High-impedance state, these ports need to be set to quasi-bidirectional
// port or strong push-pull mode for normal use
// Related IO: P0.6/P0.7/P1.6/P1.7/P2.1/P2.2
// P2.3/P2.7/P3.7/P4.2/P4.4/P4.5
/////////////////////////////////////////////////
/////////////////////////////////////////////////
// After including this header file, there is no need to include "REG51.H"
/////////////////////////////////////////////////
// Kernel Special Function Registers
__sfr __at (0xE0) ACC; // 0000,0000 accumulator
__sfr __at (0xF0) B; // 0000,0000 b register
__sfr __at (0x81) SP; // 0000,0111 stack pointer
__sfr __at (0xD0) PSW; // 0000,0000 program status word
__sbit __at (0xD7) CY; // carry flag
__sbit __at (0xD6) AC; // auxilliary carry flag
__sbit __at (0xD5) F0; // flag 0 (user-defined)
__sbit __at (0xD4) RS1; // register bank select control bit 1
__sbit __at (0xD3) RS0; // register bank select control bit 2
__sbit __at (0xD2) OV; // overflow flag
__sbit __at (0xD1) F1; // flag 1 (user-defined)
__sbit __at (0xD0) P; // parity flag
__sfr __at (0x83) DPH; // 0000,0000 data pointer high byte
__sfr __at (0x82) DPL; // 0000,0000 data pointer low byte
__sfr16 __at (0x8382) DP_16; // 0000,0000,0000,0000 data pointer
// I/O Special Function Registers
__sfr __at (0x93) P0M1; // 0000,0000 port 0 mode register 1
__sfr __at (0x94) P0M0; // 0000,0000 port 0 mode register 0
__sfr __at (0x80) P0; // 1111,1111 port 0
__sbit __at (0x87) P07; // port 0 pin 7
__sbit __at (0x86) P06; // port 0 pin 6
__sbit __at (0x85) P05; // port 0 pin 5
__sbit __at (0x84) P04; // port 0 pin 4
__sbit __at (0x83) P03; // port 0 pin 3
__sbit __at (0x82) P02; // port 0 pin 2
__sbit __at (0x81) P01; // port 0 pin 1
__sbit __at (0x80) P00; // port 0 pin 0
__sfr __at (0x91) P1M1; // 0000,0000 port 1 mode register 1
__sfr __at (0x92) P1M0; // 0000,0000 port 1 mode register 0
__sfr __at (0x90) P1; // 1111,1111 port 1
__sbit __at (0x97) P17; // port 1 pin 7
__sbit __at (0x96) P16; // port 1 pin 6
__sbit __at (0x95) P15; // port 1 pin 5
__sbit __at (0x94) P14; // port 1 pin 4
__sbit __at (0x93) P13; // port 1 pin 3
__sbit __at (0x92) P12; // port 1 pin 2
__sbit __at (0x91) P11; // port 1 pin 1
__sbit __at (0x90) P10 // port 1 pin 0
__sfr __at (0x95) P2M1; // 0000,0000 port 2 mode register 1
__sfr __at (0x96) P2M0; // 0000,0000 port 2 mode register 0
__sfr __at (0xA0) P2; // 1111,1111 port 2
__sbit __at (0xA7) P27; // port 2 pin 7
__sbit __at (0xA6) P26; // port 2 pin 6
__sbit __at (0xA5) P25; // port 2 pin 5
__sbit __at (0xA4) P24; // port 2 pin 4
__sbit __at (0xA3) P23; // port 2 pin 3
__sbit __at (0xA2) P22; // port 2 pin 2
__sbit __at (0xA1) P21; // port 2 pin 1
__sbit __at (0xA0) P20; // port 2 pin 0
__sfr __at (0xB1) P3M1; // 0000,0000 port 3 mode register 1
__sfr __at (0xB2) P3M0; // 0000,0000 port 3 mode register 0
__sfr __at (0xB0) P3; // 1111,1111 port 3
__sbit __at (0xB7) P37; // port 3 pin 7
__sbit __at (0xB6) P36; // port 3 pin 6
__sbit __at (0xB5) P35; // port 3 pin 5
__sbit __at (0xB4) P34; // port 3 pin 4
__sbit __at (0xB3) P33; // port 3 pin 3
__sbit __at (0xB2) P32; // port 3 pin 2
__sbit __at (0xB1) P31; // port 3 pin 1
__sbit __at (0xB0) P30; // port 3 pin 0
__sfr __at (0xB3) P4M1; // 0000,0000 port 4 mode register 1
__sfr __at (0xB4) P4M0; // 0000,0000 port 4 mode register 0
__sfr __at (0xC0) P4; // 1111,1111 port 4
__sbit __at (0xC7) P47; // port 4 pin 7
__sbit __at (0xC6) P46; // port 4 pin 6
__sbit __at (0xC5) P45; // port 4 pin 5
__sbit __at (0xC4) P44; // port 4 pin 4
__sbit __at (0xC3) P43; // port 4 pin 3
__sbit __at (0xC2) P42; // port 4 pin 2
__sbit __at (0xC1) P41; // port 4 pin 1
__sbit __at (0xC0) P40; // port 4 pin 0
__sfr __at (0xC9) P5M1; // 0000,0000 port 5 mode register 1
__sfr __at (0xCA) P5M0; // 0000,0000 port 5 mode register 0
__sfr __at (0xC8) P5; // xxxx,1111 port 5
__sbit __at (0xCF) P57; // port 5 pin 7
__sbit __at (0xCE) P56; // port 5 pin 6
__sbit __at (0xCD) P55; // port 5 pin 5
__sbit __at (0xCC) P54; // port 5 pin 4
__sbit __at (0xCB) P53; // port 5 pin 3
__sbit __at (0xCA) P52; // port 5 pin 2
__sbit __at (0xC9) P51; // port 5 pin 1
__sbit __at (0xC8) P50; // port 5 pin 0
__sfr __at (0xCB) P6M1; // 0000,0000 port 6 mode register 1
__sfr __at (0xCC) P6M0; // 0000,0000 port 6 mode register 0
__sfr __at (0xE8) P6; // 0000,0000 port 6
__sbit __at (0xEF) P67; // port 6 pin 7
__sbit __at (0xEE) P66; // port 6 pin 6
__sbit __at (0xED) P65; // port 6 pin 5
__sbit __at (0xEC) P64; // port 6 pin 4
__sbit __at (0xEB) P63; // port 6 pin 3
__sbit __at (0xEA) P62; // port 6 pin 2
__sbit __at (0xE9) P61; // port 6 pin 1
__sbit __at (0xE8) P60; // port 6 pin 0
__sfr __at (0xE1) P7M1; // 0000,0000 port 7 mode register 1
__sfr __at (0xE2) P7M0; // 0000,0000 port 7 mode register 0
__sfr __at (0xF8) P7; // 0000,0000 port 7
__sbit __at (0xFF) P77; // port 7 pin 7
__sbit __at (0xFE) P76; // port 7 pin 6
__sbit __at (0xFD) P75; // port 7 pin 5
__sbit __at (0xFC) P74; // port 7 pin 4
__sbit __at (0xFB) P73; // port 7 pin 3
__sbit __at (0xFA) P72; // port 7 pin 2
__sbit __at (0xF9) P71; // port 7 pin 1
__sbit __at (0xF8) P70; // port 7 pin 0
// System Management Special Function Registers
__sfr __at (0x87) PCON; // 0001,0000 power control register
#define SMOD 0x80 // double baud rate of UART
#define SMOD0 0x40 // SM0/FE bit select
#define LVDF 0x20 // low voltage flag
#define POF 0x10 // power-on flag
#define GF1 0x08 // general purpose flag 1
#define GF0 0x04 // general purpose flag 0
#define PD 0x02 // stop mode / power-down
#define IDL 0x01 // idle mode
__sfr __at (0x8E) AUXR; // 0000,0000 auxiliary register
#define T0X12 0x80 // timer 0 clock source
#define T1X12 0x40 // timer 1 clock source
#define UART_M0X6 0x20 // UART 1 baud rate select under mode 0
#define T2R 0x10 // timer 2 run control
#define T2_CT 0x08 // counter / timer 2 select
#define T2X12 0x04 // timer 2 clock source
#define EXTRAM 0x02 // internal / external RAM access control
#define S1ST2 0x01 // UART 1 baud rate source (timer 1 / timer 2)
__sfr __at (0xA2) AUXR1; // 0000,0000 auxiliary register 2
__sfr __at (0xA2) P_SW1; // 0000,0000 peripheral port switch register 1
#define S1_S1 0x80 // UART 1 pin select control bit 1
#define S1_S0 0x40 // UART 1 pin select control bit 0
#define CCP_S1 0x20 // CCP pin select control bit 1
#define CCP_S0 0x10 // CCP pin select control bit 0
#define SPI_S1 0x08 // SPI pin select control bit 1
#define SPI_S0 0x04 // SPI pin select control bit 0
// bit 1 is unused
#define DPS 0x01 // data pointer select
__sfr __at (0x97) CLK_DIV; // 0000,0000 clock divider control register
__sfr __at (0x97) PCON2; // 0000,0000 power control register 2
#define MCKO_S1 0x80 // master clock output division bit 1
#define MCKO_S0 0x40 // master clock output division bit 0
#define ADRJ 0x20 // ADC result right justification
#define TX_RX 0x10 // UART 1 relay and broadcast mode
#define MCLKO_2 0x08 // master clock output pin select
#define CLKS2 0x04 // master to system clock divisor bit 2
#define CLKS1 0x02 // master to system clock divisor bit 1
#define CLKS0 0x01 // master to system clock divisor bit 0
__sfr __at (0xA1) BUS_SPEED; // xx10,x011 bus speed control register
// bits 7 to 2 are unused
#define EXRTS1 0x02 // extended RAM timing select bit 1
#define EXTRS0 0x01 // extended RAM timing select bit 0
__sfr __at (0x9D) P1ASF; // 0000,0000 port 1 analog function configuration register
#define P17ASF 0x80 // P1.7 GPIO / ADC select
#define P16ASF 0x40 // P1.6 GPIO / ADC select
#define P15ASF 0x20 // P1.5 GPIO / ADC select
#define P14ASF 0x10 // P1.4 GPIO / ADC select
#define P13ASF 0x08 // P1.3 GPIO / ADC select
#define P12ASF 0x04 // P1.2 GPIO / ADC select
#define P11ASF 0x02 // P1.1 GPIO / ADC select
#define P10ASF 0x01 // P1.0 GPIO / ADC select
__sfr __at (0xBA) P_SW2; // 0000,0000 peripheral port switch register 2
#define EAXSFR 0x80 // data pointer access XRAM / XSFR
#define DBLPWR 0x40 // ???
#define PWM67_S 0x20 // PWM 6 and 7 pin select
#define PWM2345_S 0x10 // PWM 2, 3, 4 and 5 pin select
// bit 3 is unused
#define S4_S 0x04 // UART 4 pin select
#define S3_S 0x02 // UART 3 pin select
#define S2_S 0x01 // UART 2 pin select
// Interrupt Enable Special Function Register
__sfr __at (0xA8) IE; // 0000,0000 interrupt control register
__sbit __at (0xAF) EA; // enable/disable all
__sbit __at (0xAE) ELVD; // low voltage detection
__sbit __at (0xAD) EADC; // analog to digital converter
__sbit __at (0xAC) ES; // serial port 1
__sbit __at (0xAB) ET1; // timer 1
__sbit __at (0xAA) EX1; // external 1
__sbit __at (0xA9) ET0; // timer 0
__sbit __at (0xA8) EX0; // external 0
// Interrupt Priority Special Function Register
__sfr __at (0xB8) IP; // 0000,0000 interrupt priority register
__sbit __at (0xBF) PPCA; // programmable counter array
__sbit __at (0xBE) PLVD; // low voltage detection
__sbit __at (0xBD) PADC; // analog to digital converter
__sbit __at (0xBC) PS1; // serial port 1
__sbit __at (0xBB) PT1; // timer 1
__sbit __at (0xBA) PX1; // external 1
__sbit __at (0xB9) PT0; // timer 0
__sbit __at (0xB8) PX0; // external 0
// Interrupt Enable Special Function Register 2
__sfr __at (0xAF) IE2; // 0000,0000 interrupt control register 2
// bit 7 is unused
#define ET4 0x40 // timer 4
#define ET3 0x20 // timer 3
#define ES4 0x10 // serial port 4
#define ES3 0x08 // serial port 3
#define ET2 0x04 // timer 2
#define ESP1 0x02 // SPI
#define ES2 0x01 // serial port 2
// Interrupt Priority Special Function Register 2
__sfr __at (0xB5) IP2; // xxxx,xx00 interrupt priority register 2
// bits 7 to 2 are unused
#define PSPI // SPI
#define PS2 // serial port 2
__sfr __at (0x8F) INT_CLKO; // 0000,0000 external interrupt and clock output control register
__sfr __at (0x8F) AUXR2; // 0000,0000 external interrupt and clock output control register
// bit 7 is unused
#define EX4 0x40 // ???
#define EX3 0x20 // ???
#define EX2 0x10 // ???
// bit 3 is unused
#define T2CLKO 0x04 // P3.0 timer 2 clock output
#define T1CLKO 0x02 // P3.4 timer 1 clock output
#define T0CLKO 0x01 // P3.5 timer 0 clock output
// Timer Special Function Register
__sfr __at (0x88) TCON; // 0000,0000 T0/T1 control register
__sbit __at (0x8F) TF1; // timer / counter 1 overflow flag
__sbit __at (0x8E) TR1; // timer / counter 1 run control
__sbit __at (0x8D) TF0; // timer / counter 0 overflow flag
__sbit __at (0x8C) TR0; // timer / counter 0 run control
__sbit __at (0x8B) IE1; // external interrupt 1 request flag
__sbit __at (0x8A) IT1; // external interrupt 1 type
__sbit __at (0x89) IE0; // external interrupt 0 request flag
__sbit __at (0x88) IT0; // external interrupt 0 type
__sfr __at (0x89) TMOD; // 0000,0000 T0/T1 mode register
#define T1GATE 0x80 // timer / counter 1 gate control
#define T1CT 0x40 // timer / counter 1 select
#define T1M1 0x20 // timer 1 mode bit 1
#define T1M0 0x10 // timer 1 mode bit 0
#define T0GATE 0x08 // timer / counter 0 gate control
#define T0CT 0x04 // timer / counter 0 select
#define T0M1 0x02 // timer 0 mode bit 1
#define T0M0 0x01 // timer 0 mode bit 0
__sfr __at (0x8C) TH0; // 0000,0000 T0 high byte
__sfr __at (0x8A) TL0; // 0000,0000 T0 low byte
__sfr __at (0x8C8A) T0_16; // 0000,0000,0000,0000 T0
__sfr __at (0x8D) TH1; // 0000,0000 T1 high byte
__sfr __at (0x8B) TL1; // 0000,0000 T1 low byte
__sfr __at (0x8D8B) T1_16; // 0000,0000,0000,0000 T1
__sfr __at (0xD1) T4T3M; // 0000,0000 T3/T4 mode register
__sfr __at (0xD1) T3T4M; // 0000,0000 T3/T4 mode register
#define T4R 0x80 // timer / counter 4 run control
#define T4CT 0x40 // timer / counter 4 select
#define T4X12 0x20 // timer 4 clock source
#define T4CLKO 0x10 // P0.6 timer 4 clock output
#define T3R 0x08 // timer / counter 3 run control
#define T3CT 0x04 // timer / counter 3 select
#define T3X12 0x02 // timer 3 clock source
#define T3CLKO 0x01 // P0.4 timer 3 clock output
__sfr __at (0xD2) T4H; // 0000,0000 T4 high byte
__sfr __at (0xD3) T4L; // 0000,0000 T4 low byte
__sfr16 __at (0xD2D3) T4_16; // 0000,0000,0000,0000 T4
__sfr __at (0xD4) T3H; // 0000,0000 T3 high byte
__sfr __at (0xD5) T3L; // 0000,0000 T3 low byte
__sfr16 __at (0xD4D3) T3_16; // 0000,0000,0000,0000 T3
__sfr __at (0xD6) T2H; // 0000,0000 T2 high byte
__sfr __at (0xD7) T2L; // 0000,0000 T2 low byte
__sfr16 __at (0xD6D7) T2_16; // 0000,0000,0000,0000 T2
__sfr __at (0xAB) WKTCH; // 0000,0000 power-down wake-up timer high byte
__sfr __at (0xAA) WKTCL; // 0000,0000 power-down wake-up timer low byte
__sfr16 __at (0xABAA) WKTC_16; // 0000,0000,0000,0000 power-down wake-up timer
__sfr __at (0xC1) WDT_CONTR; // 0000,0000 watchdog control register
#define WDT_FLAG 0x80 // watch-dog timer reset flag
// bit 6 is unused
#define EN_WDT 0x20 // enable watch-dog timer
#define CLR_WDT 0x10 // watch-dog timer clear
#define IDLE_WDT 0x08 // enable watch-dog timer in idle mode
#define PS2 0x04 // watch-dog timer prescaler bit 2
#define PS1 0x02 // watch-dog timer prescaler bit 1
#define PS0 0x01 // watch-dog timer prescaler bit 0
// Serial Port Special Function Register
__sfr __at (0x99) SBUF; // xxxx,xxxx serial port 1 data register
__sfr __at (0x98) SCON; // 0000,0000 serial port 1 control register
__sbit __at (0x9F) SM0; // serial port mode bit 0 / framing error flag
__sbit __at (0x9E) SM1; // serial port mode bit 1
__sbit __at (0x9D) SM2; // serial port mode bit 2
__sbit __at (0x9C) REN; // enable serial port reception
__sbit __at (0x9B) TB8; // mode 2 and 3 9th transmit bit
__sbit __at (0x9A) RB8; // mode 2 and 3 9th receive bit
__sbit __at (0x99) TI; // transmit complete interrupt flag
__sbit __at (0x98) RI; // receive complete interrupt flag
__sfr __at (0x9B) S2BUF; // xxxx,xxxx serial 2 data register
__sfr __at (0x9A) S2CON; // 0000,0000 serial port 2 control register
#define S2SM0 0x80 // serial port 2 mode
// bit 6 is unused
#define S2SM2 0x20 // enable automatic address recognition
#define S2REN 0x10 // enable serial port reception
#define S2TB8 0x08 // mode 1 9th transmit bit
#define S2RB8 0x04 // mode 1 9th receive bit
#define S2TI 0x02 // transmit complete interrupt flag
#define S2RI 0x01 // receive complete interrupt flag
__sfr __at (0xAD) S3BUF; // xxxx,xxxx serial 3 data register
__sfr __at (0xAC) S3CON; // 0000,0000 serial 3 control register
#define S3SM0 0x80 // serial port 3 mode
#define S3ST3 0x40 // baud-rate from timer 2 / timer 3
#define S3SM2 0x20 // enable automatic address recognition
#define S3REN 0x10 // enable serial port reception
#define S3TB8 0x08 // mode 1 9th transmit bit
#define S3RB8 0x04 // mode 1 9th receive bit
#define S3TI 0x02 // transmit complete interrupt flag
#define S3RI 0x01 // receive complete interrupt flag
__sfr __at (0x85) S4BUF; // xxxx,xxxx serial 4 data register
__sfr __at (0x84) S4CON; // 0000,0000 serial 4 control register
#define S4SM0 0x80 // serial port 4 mode
#define S4ST4 0x40 // baud-rate from timer 2 / timer 4
#define S3SM2 0x20 // enable automatic address recognition
#define S4REN 0x10 // enable serial port reception
#define S4TB8 0x08 // mode 1 9th transmit bit
#define S4RB8 0x04 // mode 1 9th receive bit
#define S4TI 0x02 // transmit complete interrupt flag
#define S4RI 0x01 // receive complete interrupt flag
__sfr __at (0xA9) SADDR; // 0000,0000 slave address register
__sfr __at (0xB9) SADEN; // 0000,0000 slave address mask register
// ADC Special Function Register
__sfr __at (0xBC) ADC_CONTR; // 0000,0000 A/D conversion control register
#define ADC_POWER 0x80 // enable ADC block power
#define SPEED1 0x40 // conversion speed bit 1
#define SPEED0 0x20 // conversion speed bit 0
#define ADC_FLAG 0x10 // conversion complete interrupt flag
#define ADC_START 0x08 // start conversion
#define CHS2 0x04 // analog input channel bit 2
#define CHS1 0x02 // analog input channel bit 1
#define CHS0 0x01 // analog input channel bit 0
__sfr __at (0xBD) ADC_RES; // 0000,0000 A/D high 8 bits of conversion result
__sfr __at (0xBE) ADC_RESL; // 0000,0000 A/D low 2 bits of conversion result
__sfr16 __at (0xBDBE) ADC_RES_16; // 0000,0000,0000,0000 A/D conversion result
// SPI Special Function Register
__sfr __at (0xCD) SPSTAT; // 00xxx,xxx SPI status register
#define SPIF 0x80 // transfer complete interrupt flag
#define WCOL 0x40 // write collision flag
// bits 5 to 0 are unused
__sfr __at (0xCE) SPCTL; // 0000,0100 SPI control register
#define SSIG 0x80 // ignore slave select pin
#define SPEN 0x40 // enable SPI
#define DORD 0x20 // data bit order
#define MSTR 0x10 // master / slave mode
#define CPOL 0x08 // clock polarity
#define CPHA 0x04 // clock phase
#define SPR1 0x02 // clock rate bit 1
#define SPR0 0x01 // clock rate bit 0
__sfr __at (0xCF) SPDAT; // 0000,0000 SPI data register
// IAP/ISP Special Function Register
__sfr __at (0xC7) IAP_CONTR; // 0000,x000 EEPROM control register
#define IAPEN 0x80 // enable ISP / IAP operation
#define SWBS 0x40 // software boot selection
#define SWRST 0x20 // software reset trigger
#define CMD_FAIL 0x10 // ISP / IAP command failure flag
// bit 3 is unused
#define WT2 0x04 // waiting time bit 2
#define WT1 0x02 // waiting time bit 1
#define WT0 0x01 // waiting time bit 0
__sfr __at (0xC5) IAP_CMD; // xxxx,xx00 EEPROM command register
// bits 7 to 2 are unused
#define MS1 0x02 // ISP / IAP operating mode bit 1
#define MS0 0x01 // ISP / IAP operating mode bit 0
__sfr __at (0xC6) IAP_TRIG; // 0000,0000 EEPROM command trigger register
__sfr __at (0xC2) IAP_DATA; // 0000,0000 EEPROM data register
__sfr __at (0xC3) IAP_ADDRH; // 0000,0000 EEPROM address high byte
__sfr _at (0xC4) IAP_ADDRL; // 0000,0000 EEPROM address low byte
__sfr16 __at (0xC3C4) IAP_ADDR_16; // 0000,0000,0000,0000 EEPROM address
// PCA/PWM Special Function Register
__sfr __at (0xD8) CCON; // 00xx,xx00 PCA control register
__sbit __at (0xDF) CF; // counter overflow flag
__sbit __at (0xDE) CR; // counter run control
// bits 5 to 3 are unused
__sbit __at (0xDA) CCF2; // module 2 interrupt flag
__sbit __at (0xD9) CCF1; // module 1 interrupt flag
__sbit __at (0xD8) CCF0; // module 0 interrupt flag
__sfr __at (0xD9) CMOD; // 0xxx,x000 PCA working mode register
#define CIDL 0x80 // disable counter in idle mode
// bits 6 to 4 are unused
#define CPS2 0x08 // counter pulse source bit 2
#define CPS1 0x04 // counter pulse source bit 1
#define CPS0 0x02 // counter pulse source bit 0
#define ECF 0x01 // counter overflow interrupt flag
__sfr __at (0xF9) CH; // 0000,0000 PCA counter high byte
__sfr __at (0xE9) CL; // 0000,0000 PCA counter low byte
__sfr16 __at (0xF9E9) C_16; // 0000,0000,0000,0000 PCA counter
__sfr __at (0xFA) CCAP0H; // 0000,0000 PCA module 0 capture/compare register high byte
__sfr __at (0xEA) CCAP0L; // 0000,0000 PCA module 0 capture/compare register low byte
__sfr16 __at (0xFAEA) CCAP0_16; // 0000,0000,0000,0000 PCA module 0 capture/compare register
__sfr __at (0xDA) CCAPM0; // 0000,0000 PCA PWM register of module 0
// bit 7 is unused
#define ECOM0 0x40 // enable comparator
#define CAPP0 0x20 // capture positive edge
#define CAPN0 0x10 // capture negative edge
#define MAT0 0x08 // match control
#define TOG0 0x04 // toggle control
#define PWM0 0x02 // pulse width modulation
#define ECCF0 0x01 // enable CCF0 interrupt
__sfr __at (0xF2) PCA_PWM0; // xxxx,xx00 PCA PWM register of module 0
#define EBS0_1 0x80 // function select bit 1
#define EBS0_0 0x40 // function select bit 0
// bits 5 to 2 are unused
#define EPC0H 0x02 // ???
#define EPC0L 0x01 // ???
__sfr __at (0xFB) CCAP1H; // 0000,0000 PCA module 1 capture/compare register high byte
__sfr __at (0xEB) CCAP1L; // 0000,0000 PCA module 1 capture/compare register low byte
__sfr __at (0xFBEB) CCAP1_16; // 0000,0000,0000,0000 PCA module 1 capture/compare register
__sfr __at (0xDB) CCAPM1; // 0000,0000 PCA PWM register of module 1
// bit 7 is unused
#define ECOM1 0x40 // enable comparator
#define CAPP1 0x20 // capture positive edge
#define CAPN1 0x10 // capture negative edge
#define MAT1 0x08 // match control
#define TOG1 0x04 // toggle control
#define PWM1 0x02 // pulse width modulation
#define ECCF1 0x01 // enable CCF1 interrupt
__sfr __at (0xF3) PCA_PWM1; // xxxx,xx00 PCA PWM register of module 1
#define EBS1_1 0x80 // function select bit 1
#define EBS1_0 0x40 // function select bit 0
// bits 5 to 2 are unused
#define EPC1H 0x02 // ???
#define EPC1L 0x01 // ???
__sfr __at (0xFC) CCAP2H; // 0000,0000 PCA module 2 capture/compare register high byte
__sfr __at (0xEC) CCAP2L; // 0000,0000 PCA module 2 capture/compare register low byte
__sfr16 __at (0xFCEC) CCAP2_16; // 0000,0000,0000,0000 PCA module 2 capture/compare register
__sfr __at (0xDC) CCAPM2; // 0000,0000 PCA PWM register of module 2
// bit 7 is unused
#define ECOM2 0x40 // enable comparator
#define CAPP2 0x20 // capture positive edge
#define CAPN2 0x10 // capture negative edge
#define MAT2 0x08 // match control
#define TOG2 0x04 // toggle control
#define PWM2 0x02 // pulse width modulation
#define ECCF2 0x01 // enable CCF2 interrupt
__sfr __at (0xF4) PCA_PWM2; // xxxx,xx00 PCA PWM register of module 2
#define EBS2_1 0x80 // function select bit 1
#define EBS2_0 0x40 // function select bit 0
// bits 5 to 2 are unused
#define EPC2H 0x02 // ????
#define EPC2L 0x01 // ???
// Comparator Special Function Register
__sfr __at (0xE6) CMPCR1; // 0000,0000 comparator control register 1
#define CMPEN 0x80 // enable comparator
#define CMPIF 0x40 // interrupt flag
#define PIE 0x20 // enable positive edge interrupt
#define NIE 0x10 // enable negative edge interrupt
#define PIS 0x08 // comparator positive pole select
#define NIS 0x04 // comparator negative pole select
#define CMPOE 0x02 // P1.2 comparator output enable
#define CMPRES 0x01 // comparator result flag
__sfr __at (0xE7) CMPCR2; // 0000,0000 comparator control register 2
#define CMPCR2 0x80 // inverse comparator output
#define DISFLT 0x40 // disable 100nS filter
#define LCDTY5 0x20 // duty of level-change control filter bit 5
#define LCDTY4 0x10 // duty of level-change control filter bit 4
#define LCDTY3 0x08 // duty of level-change control filter bit 3
#define LCDTY2 0x04 // duty of level-change control filter bit 2
#define LCDTY1 0x02 // duty of level-change control filter bit 1
#define LCDTY0 0x01 // duty of level-change control filter bit 0
// Enhanced PWM Waveform Generator Special Function Register
__sfr __at (0xF1) PWMCFG; // x000,0000 PWM configuration register
// bit 7 is unused
#define CBTADC 0x40 // enable ADC conversion on PWM zero
#define C7INI 0x20 // initial level of PWM7 output ports
#define C6INI 0x10 // initial level of PWM6 output ports
#define C5INI 0x08 // initial level of PWM5 output ports
#define C4INI 0x04 // initial level of PWM4 output ports
#define C3INI 0x02 // initial level of PWM3 output ports
#define C2INI 0x01 // initial level of PWM2 output ports
__sfr __at (0xF5) PWMCR; // 0000,0000 PWM control register
#define ENPWM 0x80 // enable enhanced PWM generators
#define ECBI 0x40 // enable interrupt on PWM counter zero
#define ENC7O 0x20 // enable PWM7 output ports
#define ENC6O 0x10 // enable PWM6 output ports
#define ENC5O 0x08 // enable PWM5 output ports
#define ENC4O 0x04 // enable PWM4 output ports
#define ENC3O 0x02 // enable PWM3 output ports
#define ENC2O 0x01 // enable PWM2 output ports
__sfr __at (0xF6) PWMIF; // x000,0000 PWM interrupt flag register
// bit 7 is unused
#define CBIF 0x40 // PWM counter zero interrupt flag
#define C7IF 0x20 // PWM7 interrupt flag
#define C6IF 0x10 // PWM6 interrupt flag
#define C5IF 0x08 // PWM5 interrupt flag
#define C4IF 0x04 // PWM4 interrupt flag
#define C3IF 0x02 // PWM3 interrupt flag
#define C2IF 0x01 // PWM2 interrupt flag
__sfr __at (0xF7) PWMFDCR; // xx00,0000 PWM external anomaly detection control register
// bits 7 to 6 are unused
#define ENFD 0x20 // enable PWM exception detection
#define FLTFLIO 0x10 // PWM output port mode on external exception
#define EFDI 0x08 // enable PWM exception interrupt
#define FDCMP 0x04 // set comparator output as external exception source
#define FDIO 0x02 // set the level of P2.4 output as external exception source
#define FDIF 0x01 // PWM exception interrupt flag
// The following special function registers are located in the extended RAM area
// To access these registers, you need to set bit 7 of P_SW2 to 1, before they can read and written
__xdata volatile unsigned char __at (0xfff0) PWMCH; // x000,0000 PWM counter high byte
__xdata volatile unsigned char __at (0xfff1) PWMCL; // 0000,0000 PWM counter low byte
__xdata volatile unsigned int __at (0xfff0) PWMC; // x000,0000,0000,0000 PWM counter
__xdata volatile unsigned char __at (0xfff2) PWMCKS; // xxx0,0000 PWM clock selection
// bits 7 to 5 are unused
#define SELT2 0x10 // ???
#define PS3 0x08 // prescaler bit 3
#define PS2 0x04 // prescaler bit 2
#define PS1 0x02 // prescaler bit 1
#define PS0 0x01 // prescaler bit 0
__xdata volatile unsigned char __at (0xff00) PWM2T1H; // x000,0000 timer 1 of PWM2 high byte
__xdata volatile unsigned char __at (0xff01) PWM2T1L; // 0000,0000 timer 1 of PWM2 low byte
__xdata volatile unsigned int __at (0xFF00) PWM2T1; // x000,0000,0000,0000 timer 1 of PWM2
__xdata volatile unsigned char __at (0xff02) PWM2T2H; // x000,0000 timer 2 of PWM2 high byte
__xdata volatile unsigned char __at (0xff03) PWM2T2L; // 0000,0000 timer 2 of PWM2 low byte
__xdata volatile unsigned int __at (0xff02) PWM2T2; // x000,0000,0000,0000 timer 2 of PWM2
__xdata volatile unsigned char __at (0xff04) PWM2CR; // xxxx,0000 PWM2 control register
// bits 7 to 4 are unused
#define PWM2_PS 0x08 // output port select
#define EPW2I 0x04 // enable PWM2 interrupt
#define EC2T2SI 0x02 // enable PWM2 T2 interrupt
#define EC2T1SI 0x01 // enable PWM2 T1 interrupt
__xdata volatile unsigned char __at (0xff10) PWM3T1H; // x000,0000 timer 1 of PWM3 high byte
__xdata volatile unsigned char __at (0xff11) PWM3T1L; // 0000,0000 timer 1 of PWM3 low byte
__xdata volatile unsigned int __at (0xff10) PWM3T1; // x000,0000,0000,0000 timer 1 of PWM3
__xdata volatile unsigned char __at (0xff12) PWM3T2H; // x000,0000 timer 2 of PWM3 high byte
__xdata volatile unsigned char __at (0xff13) PWM3T2L; // 0000,0000 timer 2 of PWM3 low byte
__xdata volatile unsigned int __at (0xff12) PWM3T2; // x000,0000,0000,0000 timer 2 of PWM3
__xdata volatile unsigned char __at (0xff14) PWM3CR; // xxxx,0000 PWM3 control register
// bits 7 to 4 are unused
#define PWM3_PS 0x08 // output port select
#define EPW3I 0x04 // enable PWM3 interrupt
#define EC3T2SI 0x02 // enable PWM3 T2 interrupt
#define EC3T1SI 0x01 // enable PWM3 T1 interrupt
__xdata volatile unsigned char __at (0xff20) PWM4T1H; // x000,0000 timer 1 of PWM4 high byte
__xdata volatile unsigned char __at (0xff21) PWM4T1L; // 0000,0000 timer 1 of PWM4 low byte
__xdata volatile unsigned int __at (0xff20) PWM4T1; // x000,0000,0000,0000 timer 1 of PWM4
__xdata volatile unsigned char __at (0xff22) PWM4T2H; // x000,0000 timer 2 of PWM4 high byte
__xdata volatile unsigned char __at (0xff23) PWM4T2L; // 0000,0000 timer 2 of PWM4 low byte
__xdata volatile unsigned int __at (0xff22) PWM4T2; // x000,0000,0000,0000 timer 2 of PWM4
__xdata volatile unsigned char __at (0xff24) PWM4CR; // xxxx,0000 PWM4 control register
// bits 7 to 4 are unused
#define PWM4_PS 0x08 // output port select
#define EPW4I 0x04 // enable PWM4 interrupt
#define EC4T2SI 0x02 // enable PWM4 T2 interrupt
#define EC4T1SI 0x01 // enable PWM4 T1 interrupt
__xdata volatile unsigned char __at (0xff30) PWM5T1H; // x000,0000 timer 1 of PWM5 high byte
__xdata volatile unsigned char __at (0xff31) PWM5T1L; // 0000,0000 timer 1 of PWM5 low byte
__xdata volatile unsigned char __at (0xff30) PWM5T1; // x000,0000,0000,0000 timer 1 of PWM5
__xdata volatile unsigned char __at (0xff32) PWM5T2H; // x000,0000 timer 2 of PWM5 high byte
__xdata volatile unsigned char __at (0xff33) PWM5T2L; // 0000,0000 timer 2 of PWM5 low byte
__xdata volatile unsigned int __at (0xff32) PWM5T2; // x000,0000,0000,0000 timer 2 of PWM5
__xdata volatile unsigned char __at (0xff34) PWM5CR; // xxxx,0000 PWM5 control register
// bits 7 to 4 are unused
#define PWM5_PS 0x08 // output port select
#define EPW5I 0x04 // enable PWM5 interrupt
#define EC5T2SI 0x02 // enable PWM5 T2 interrupt
#define EC5T1SI 0x01 // enable PWM5 T1 interrupt
__xdata volatile unsigned char __at (0xff40) PWM6T1H; // x000,0000 timer 1 of PWM6 high byte
__xdata volatile unsigned char __at (0xff41) PWM6T1L; // 0000,0000 timer 1 of PWM6 low byte
__xdata volatile unsigned int __at (0xff40) PWM6T1; // x000,0000,0000,0000 timer 1 of PWM6
__xdata volatile unsigned char __at (0xff42) PWM6T2H; // x000,0000 timer 2 of PWM6 high byte
__xdata volatile unsigned char __at (0xff43) PWM6T2L; // 0000,0000 timer 2 of PWM6 low byte
__xdata volatile unsigned int __at (0xff42) PWM6T2; // x000,0000,0000,0000 timer 2 of PWM6
__xdata volatile unsigned char __at (0xff44) PWM6CR; // xxxx,0000 PWM6 control register
// bits 7 to 4 are unused
#define PWM6_PS 0x08 // output port select
#define EPWM6I 0x04 // enable PWM6 interrupt
#define EC6T2SI 0x02 // enable PWM6 T2 interrupt
#define EC6T1SI 0x01 // enable PWM6 T1 interrupt
__xdata volatile unsigned char __at (0xff50) PWM7T1H; // x000,0000 timer 1 of PWM7 high byte
__xdata volatile unsigned char __at (0xff51) PWM7T1L; // 0000,0000 timer 1 of PWM7 low byte
__xdata volatile unsigned int __at (0xff50) PWM7T1; // x000,0000,0000,0000 timer 1 of PWM7
__xdata volatile unsigned char __at (0xff52) PWM7T2H; // x000,0000 timer 2 of PWM7 high byte
__xdata volatile unsigned char __at (0xff53) PWM7T2L; // 0000,0000 timer 2 of PWM7 low byte
__xdata volatile unsigned int __at (0xff52) PWM7T2; // x000,0000,0000,0000 timer 2 of PWM7
__xdata volatile unsigned char __at (0xff54) PWM7CR; // xxxx,0000 PWM7 control register
// bits 7 to 4 are unused
#define PWM7_PS 0x08 // output port select
#define EPWM7I 0x04 // enable PWM7 interrupt
#define EC7T2SI 0x02 // enable PWM7 T2 interrupt
#define EC7T1SI 0x01 // enable PWM7 T1 interrupt
// Interrupt Vectors: address = (number * 8) + 3
#define IE0_VECTOR 0 // 0x03 external interrupt 0
#define TF0_VECTOR 1 // 0x0b timer 0
#define IE1_VECTOR 2 // 0x13 external interrupt 1
#define TF1_VECTOR 3 // 0x1b timer 1
#define SI1_VECTOR 4 // 0x23 serial port 1
#define ADC_VECTOR 5 // 0x2b analog to digital converter
#define LVD_VECTOR 6 // 0x33 low-voltage detection
#define PCA_VECTOR 7 // 0x3b programmable counter array
#define SI2_VECTOR 8 // 0x43 serial port 2
#define SPI_VECTOR 9 // 0x4b SPI interrupt
#define IE2_VECTOR 10 // 0x53 external interrupt 2
#define IE3_VECTOR 11 // 0x5b external interrupt 3
#define TF2_VECTOR 12 // 0x63 timer 2
#define PWM_VECTOR 13 // PWM interrupt
// vectors 14 to 15 are reserved
#define IE4_VECTOR 16 // 0x83 external interrupt 4
#define SI3_VECTOR 17 // 0x8b serial port 3
#define SI4_VECTOR 18 // 0x93 serial port 4
#define TF3_VECTOR 19 // 0x9b timer 3
#define TF4_VECTOR 20 // 0xa3 timer 4
#define CMP_VECTOR 21 // 0xab comparator
/////////////////////////////////////////////////
#endif