diff --git a/doc/Dependency.rst b/doc/Dependency.rst
index 0d34f303..26a126c9 100644
--- a/doc/Dependency.rst
+++ b/doc/Dependency.rst
@@ -10,7 +10,7 @@ Dependency
 .. |img-pySVModel-req-status| image:: https://img.shields.io/requires/github/edaa-org/pySystemVerilogModel
    :alt: Requires.io
    :height: 22
-   :target: https://requires.io/github/edaa-org/pySystemVerilogModel/requirements/?branch=master
+   :target: https://requires.io/github/edaa-org/pySystemVerilogModel/requirements/?branch=main
 
 +------------------------------------------+------------------------------------------+
 | `Libraries.io <https://libraries.io/>`_  | `Requires.io <https://requires.io/>`_    |
diff --git a/doc/conf.py b/doc/conf.py
index 15a3395b..70df07f4 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -224,8 +224,8 @@ def _LatestTagName():
 extlinks = {
 	'issue': ('https://github.com/edaa-org/pySystemVerilogModel/issues/%s', 'issue #'),
 	'pull':  ('https://github.com/edaa-org/pySystemVerilogModel/pull/%s', 'pull request #'),
-	'src':   ('https://github.com/edaa-org/pySystemVerilogModel/blob/master/pySystemVerilogModel/%s?ts=2', None),
-#	'test':  ('https://github.com/edaa-org/pySystemVerilogModel/blob/master/test/%s?ts=2', None)
+	'src':   ('https://github.com/edaa-org/pySystemVerilogModel/blob/main/pySystemVerilogModel/%s?ts=2', None),
+#	'test':  ('https://github.com/edaa-org/pySystemVerilogModel/blob/main/test/%s?ts=2', None)
 }