[DSLX->SystemVerilog] Output ports' names

[Muxianesty]

Greetings everyone.

I have just started using XLS, mainly DSLX-functionality, to generate pipelined computational operations in SystemVerilog.
As I understand, if we define a function with a number of parameters, a SystemVerilog module can be generated based on it: by providing --module_name-argument to codegen_main we can change the module's name, while all input ports share their names with corresponding DSLX function arguments.
However, this doesn't apply to output parameters: as I see it, out_*-naming is used for them.

So for the following example
fn ADD_FLOAT(arg1: apfloat::APFloat<8, 23>, arg2: apfloat::APFloat<8, 23>) -> apfloat::APFloat<8, 23> { let res1 = apfloat::add(arg1, arg2); res1 }
the following code can be generated
module __ADD_IN_flt_8_24_IN_flt_8_24_OUT_flt_8_24_2( input wire clk, input wire [31:0] arg1, input wire [31:0] arg2, output wire [31:0] out );

Is there any way I can manually set the output port's name, so that in the provided example res1 isn't replaced out?
Thanks in advance.

[proppy]

That's not currently possible for function, see

xls/xls/codegen/block_conversion.cc

Line 87 in f9c8c82

static const char kOutputPortName[] = "out";

Feel free to engage about this topic in the following issue: #448

[proppy]

Note: This was added in 66262cd