From e483c6a2ade2dbf2ec44d835134f62eab0cf9698 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 24 Sep 2024 21:30:16 +0200
Subject: [PATCH] Add a note about data cache.

---
 src/tusb_option.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 0d118eef9e..17de9cd72b 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -243,6 +243,10 @@
 //--------------------------------------------------------------------+
 
 // DWC2 controller: use DMA for data transfer
+// For processors with data cache enabled, USB endpoint buffer region
+// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.
+// For example, on Cortex-M7 the MPU region can be configured as normal
+// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0.
 #ifndef CFG_TUD_DWC2_DMA
   #define CFG_TUD_DWC2_DMA 0
 #endif