From a6d262796ca95c82d614ca157ce5b1f358eec945 Mon Sep 17 00:00:00 2001
From: Max Korbel <max.korbel@intel.com>
Date: Thu, 13 Feb 2025 09:19:00 -0800
Subject: [PATCH] update changelog with new bug fix

---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 8f751f91e..b710a01ec 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,6 +1,7 @@
 ## 0.6.3
 
 - Fixed a bug where `withSet` on `LogicStructure`s could sometimes attempt to access the wrong range, causing unexpected exceptions (<https://github.com/intel/rohd/pull/561>).
+- Fixed a bug where `flop` and `FlipFlop` would generate SystemVerilog with an asynchronous reset even if `asyncReset` was set to `false` (<https://github.com/intel/rohd/pull/564>).
 
 ## 0.6.2