hardware.txt

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GOL-16 HARDWARE ARCHITECTURE
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KEY SPECIFICATIONS
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- System is big-endian
- 16 bit data bus
- 16 bit address bus
- Load/Store architecture (reminiscent of ARM 32b)
- Capable of handling interrupts


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ALU OPERATIONS
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Hex | Operation | Description
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0x0 | NOOP      | Do nothing.
0x1 | ADD       | Add t1 & B input.
0x2 | SUB       | Subtract B input from t1.
0x3 | MUL       | Multiply t1 by B input.
0x4 | DIV       | Divide t1 by B input.
0x5 | AND       | Bitwise AND t1 & B input.
0x6 | OR        | Bitwise OR t1 & B input.
0x7 | NOT       | Bitwise NOT B input.
0x8 | LSL       | Logical shift t1 left by "B input" bits.
0x9 | RB        | Allows the B input to pass through the ALU.
0xA | LSR       | Logical shift t1 right by "B input" bits.
0xB | ROL       | Rotate t1 left by "B input" bits.
0xC | ROR       | Rotate t1 right by "B input" bits.
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FLAGS
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Produced by ALU:
- Carry
- Overflow
- Zero
- Negative

Additional interrupt flag, I.

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REGISTERS
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Address | Name            | Initialization Value
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0x0     | Register 0      | Anything
0x1     | Register 1      | Anything
0x2     | Register 2      | Anything
0x3     | Register 3      | Anything
0x4     | Program counter | 0x0000
0x5     | Stack pointer   | 0xFFFF
0x6     | Link register   | Anything
0x7     | Flag register   | Anything
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MEMORY MAP
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- 64KB of memory -> 0x0000 - 0xFFFF
- Stack starts from highest memory moving down
- 0x0000 -> Operating system
- 0x0001 - 0x0003 -> Interrupt subroutines
- 0x0004 - top of stack -> Heap

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INTERNAL CONTROL SIGNALS
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Name   | Description
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t1oe   | Output contents of t1 to internal data bus.
t1ce   | Write to t1 from internal data bus.
t2oe   | Output contents of t2 to internal data bus.
t2ce   | Write to t2 from alu output.
rd     | Output bits 6&7 of the instruction register onto the internal address bus.
rx     | Output bits 8&9 of the instruction register onto the internal address bus.
ry     | Output bits 10&11 of the instruction register onto the internal address bus.
ccoe   | Output bits 6-9 of the instruction register on the condition code bus.
regw   | Write data bus contents to the register on the internal address bus.
regr   | Read contents of the register on the internal address bus onto the internal data bus.
pcoe   | Output the address of the program counter onto the internal address bus.
spoe   | Output the address of the stack pointer onto the internal address bus.
lroe   | Output the address of the link register onto the internal address bus.
froe   | Output the contents of the flag register.
frce   | Write the alu flags to the flag register.
ui4    | Output zero-extended bits 12-16 of the instruction register onto the internal data bus.
ui7    | Output zero-extended bits 9-16 of the instruction register onto the internal data bus.
ui9    | Output zero-extended bits 7-16 of the instruction register onto the internal data bus.
si7    | Output sign-extended bits 9-16 of the instruction register onto the internal data bus.
si9    | Output sign-extended bits 7-16 of the instruction register onto the internal data bus.
aadd   | Assert the alu operation as add.
asub   | Assert the alu operation as subtract.
anop   | Assert NOOP to the alu.
aop    | Assert bits 2-5 of the instruction register as the alu operation.
coe    | Output the constant value 1 onto the internal data bus.
irce   | Write the contents of the data bus into the instruction register.
ctest  | Indicate that next state depends on condition code evaluation.
marce  | Write the contents of the internal data bus into register mar.
maroe  | Output the contents register mar onto the interconnection address bus.
mdrce  | Write the contents of the internal data bus into register mdr.
mdroe  | Output the contents of register mdr onto the internal data bus.
mdrput | Put the contents of the internal data bus onto the input of register mdr.
mdrget | Get the output of register mdr onto the internal data bus.
ibread | Read contents of main memory at the address on interconnection address bus onto the interconnection data bus.
ibwrite| Write contents of the interconnection data bus into main memory at address on the interconnection address bus.
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