-
Notifications
You must be signed in to change notification settings - Fork 100
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Keep higher level abstraction for runtime memory orders on atomics #743
Comments
Hi, I want to work on this issue. |
To support non-constant operand, we can consider the following approaches:
I prefer option 3 above. |
I tried to use option 3 to address this issue, but there is a problem with lowering during the LoweringPrepare phase. %expected = cir.load %expected_addr : !cir.ptr<!s32i>, !s32i
%desired = cir.load %desired_var : !cir.ptr<!s32i>, !s32i
%old, %cmp = cir.atomic.cmp_xchg(%ptr : !cir.ptr<!s32i>, %expected : !s32i, %desired : !s32i, success = relaxed, failure = relaxed) : (!s32i, !cir.bool)
%succeeded = cir.unary(not, %cmp) : !cir.bool, !cir.bool
cir.if %succeeded {
cir.store %old, %expected_addr : !s32i, !cir.ptr<!s32i>
}
cir.store %cmp, %result_var : !cir.bool, !cir.ptr<!cir.bool> If we expand the non-constant |
Sorry about the delay!
I think it might be better just to create a new operation, more clean and direct. You can refactor AtomicCmpXchg into a tablegen class (see how we implement CallOp) if you want to reuse part of the code.
This should be done in two steps:
Not sure I follow, if you are able to transform it to the constant version, why do you need a switch anyways? |
Thanks for you reply.
There are five operations that need to accept non-constant mem order. (StoreOp, LoadOp, AtomicFetch, AtomicXchg, AtomicCmpXchg). Does this make
Sorry, my example IR is confusing. What I mean is that when we cannot transform the non-constant version to the constant version, we need to lower it though a 1、%old, %cmp = cir.atomic.cmp_xchg(%ptr : !cir.ptr<!s32i>, %expected : !s32i, %desired : !s32i, success = relaxed, failure = relaxed) : (!s32i, !cir.bool)
2、%succeeded = cir.unary(not, %cmp) : !cir.bool, !cir.bool
3、cir.if %succeeded {
4、 cir.store %old, %expected_addr : !s32i, !cir.ptr<!s32i>
}
5、cir.store %cmp, %result_var : !cir.bool, !cir.ptr<!cir.bool> In |
#731 adds CIRGen support for non-constant memory orders all the way down to LLVM.
To keep CIR a bit more simple and easier to analyze, we could change atomic operations to support the non-constant version as well and do the same lowering during LoweringPrepare instead (see
clang/test/CIR/CodeGen/atomic-runtime.cpp
for the example currently generated). This also opens the possibility of folding atomic operations into the constant version once we start doing some inline in CIR.The text was updated successfully, but these errors were encountered: