From 053e479e12c3dc3bf3e42b02fdc4c73f81c793b7 Mon Sep 17 00:00:00 2001
From: datdenkikniet <jcdra1@gmail.com>
Date: Fri, 10 Feb 2023 10:20:55 +0100
Subject: [PATCH] Add some more TODOs

Panic on FBE
---
 src/dma/mod.rs    |  6 ++++++
 src/dma/rx/mod.rs | 15 +++++++--------
 src/dma/tx/mod.rs | 10 ++++++----
 src/setup.rs      |  1 -
 4 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/src/dma/mod.rs b/src/dma/mod.rs
index adc8ceac..9d2142b4 100644
--- a/src/dma/mod.rs
+++ b/src/dma/mod.rs
@@ -444,6 +444,12 @@ fn eth_interrupt_handler_impl(eth_dma: &ETHERNET_DMA) -> InterruptReasonSummary
                 .set_bit()
         });
 
+        if status.fbe().bit_is_set() {
+            // TODO: add a link to a/the github issue describing this problem,
+            // and how to solve it.
+            panic!("Fatal bus error! Is the descriptor and buffer memory accessible by the Ethernet MAC/DMA?");
+        }
+
         (
             status.ri().bit_is_set(),
             status.ti().bit_is_set(),
diff --git a/src/dma/rx/mod.rs b/src/dma/rx/mod.rs
index efcdd907..68c1d9c6 100644
--- a/src/dma/rx/mod.rs
+++ b/src/dma/rx/mod.rs
@@ -109,16 +109,15 @@ impl<'data> RxRing<'data, NotRunning> {
 
         #[cfg(feature = "stm32h7xx-hal")]
         {
-            // TODO: assert that ethernet DMA can access
-            // the memory in these rings
-            assert!(self.ring.descriptors().count() >= 4);
+            let rx_ring_descriptors = self.ring.descriptors().count();
+            assert!(rx_ring_descriptors >= 4);
 
             // Assert that the descriptors are properly aligned.
-            assert!(ring_ptr as u32 & !0b11 == ring_ptr as u32);
-            assert!(
-                self.ring.last_descriptor_mut() as *const _ as u32 & !0b11
-                    == self.ring.last_descriptor_mut() as *const _ as u32
-            );
+            //
+            // FIXME: these require different alignment if the data is stored
+            // in AXI SRAM
+            assert!(ring_ptr as u32 % 4 == 0);
+            assert!(self.ring.last_descriptor_mut() as *const _ as u32 % 4 == 0);
 
             // Set the start pointer.
             eth_dma
diff --git a/src/dma/tx/mod.rs b/src/dma/tx/mod.rs
index 8bcc8aad..3c7e63b6 100644
--- a/src/dma/tx/mod.rs
+++ b/src/dma/tx/mod.rs
@@ -114,12 +114,14 @@ impl<'data> TxRing<'data, NotRunning> {
 
         #[cfg(feature = "stm32h7xx-hal")]
         {
-            // TODO: assert that ethernet DMA can access
-            // the memory in these rings
-            assert!(self.ring.descriptors().count() >= 4);
+            let tx_descriptor_count = 0;
+            assert!(tx_descriptor_count >= 4);
 
             // Assert that the descriptors are properly aligned.
-            assert!(ring_ptr as u32 & !0b11 == ring_ptr as u32);
+            //
+            // FIXME: these require different alignment if the data is stored
+            // in AXI SRAM
+            assert!(ring_ptr as u32 % 4 == 0);
             assert!(self.ring.last_descriptor() as *const _ as u32 % 4 == 0);
 
             // Set the start pointer.
diff --git a/src/setup.rs b/src/setup.rs
index cfd0f5fc..459abacd 100644
--- a/src/setup.rs
+++ b/src/setup.rs
@@ -41,7 +41,6 @@ use crate::{
 };
 
 #[cfg(feature = "stm32h7xx-hal")]
-// TODO: implement all allowed GPIO pins.
 #[allow(unused_imports)]
 use crate::{
     dma::EthernetDMA,