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instant background change
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unknown authored and unknown committed Jul 19, 2009
1 parent b673705 commit 100410a
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Showing 4 changed files with 30 additions and 23 deletions.
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17 changes: 2 additions & 15 deletions background.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -20,12 +20,10 @@ architecture Behavioral of background is
clk25 : in bit);
end component;

signal chosen_background : STD_LOGIC_VECTOR (1 downto 0);
signal chosen_background : STD_LOGIC_VECTOR (1 downto 0);
signal rgb_farbw : STD_LOGIC_VECTOR (2 downto 0);
signal will_switch : bit;
signal deltaX : integer range 0 to 320;
signal deltaY : integer range 0 to 240;
signal count_up : integer range 0 to 25000000;
signal wobble_clock : integer range 0 to 400000 := 0;
signal wobble : integer range 0 to 64 := 32;
signal wobble_growing : bit := '1';
Expand All @@ -42,18 +40,7 @@ begin
begin

if clk25'event and clk25 = '1' then

if switch = '1' then
will_switch <= '1';
end if;
count_up <= count_up + 1;
if count_up = 25000000 then
if will_switch = '1' then
chosen_background <= chosen_background + "01";
will_switch <= '0';
end if;
count_up <= 0;
end if;
chosen_background <= chosen_background + ( '0' & switch);

case chosen_background is

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23 changes: 20 additions & 3 deletions process_keys.vhd
Original file line number Diff line number Diff line change
@@ -1,19 +1,20 @@
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity process_keys is
port (
keys_in : in std_logic_vector(13 downto 6);
keys_in : in std_logic_vector(13 downto 5);
reset: in bit;
game_over: in std_logic;
clk25: in bit;
hold_out: out std_logic;
inverse_out: out bit;
ballspeed_out : out std_logic_vector(1 downto 0);
paddlespeed_out : out bit;
AI_out: out std_logic
AI_out: out std_logic;
switch_out: out std_logic
);
end process_keys;

Expand All @@ -22,12 +23,28 @@ architecture Behavioral of process_keys is
signal set_inverse_key: std_logic := '0';
signal set_paddlespeed_key: std_logic :='0';
signal set_AI_key: std_logic := '0';
signal set_switch_key: std_logic := '0';
signal Q_hold: std_logic := '1';
signal Q_inverse: bit := '0';
signal Q_paddlespeed: bit := '0';
signal Q_AI: std_logic := '0';

begin

switch_key: process (clk25)
begin
if clk25'event and clk25='1' then
if keys_in(5)='1' and set_switch_key ='0' then
switch_out <= '1';
set_switch_key <='1';
elsif set_switch_key ='1' then
switch_out <= '0';
if keys_in(5)='0' then set_switch_key <= '0'; end if;
else switch_out <='0';
end if;
end if;
end process switch_key;

pause_key: process (clk25)
begin
if clk25'event and clk25='1' then
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13 changes: 8 additions & 5 deletions vga.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -25,15 +25,16 @@ architecture Behavioral of vga is

component process_keys
port (
keys_in : in std_logic_vector(13 downto 6);
keys_in : in std_logic_vector(13 downto 5);
reset: in bit;
game_over: in std_logic;
clk25: in bit;
hold_out: out std_logic;
inverse_out: out bit;
ballspeed_out : out std_logic_vector(1 downto 0);
paddlespeed_out : out bit;
AI_out: out std_logic
AI_out: out std_logic;
switch_out: out std_logic
);
end component;

Expand Down Expand Up @@ -141,6 +142,7 @@ architecture Behavioral of vga is
signal intermediate_ballpos : integer range 0 to 480;
signal intermediate_ai_enabled : std_logic;
signal intermediate_bar_right2 : integer range 0 to 430; -- output of AI
signal intermediate_switch_out : std_logic;

begin

Expand All @@ -167,15 +169,16 @@ begin
keysout => intermediate_keys);

verarbeite_keys : process_keys port map (
keys_in => intermediate_keys(13 downto 6),
keys_in => intermediate_keys(13 downto 5),
reset => intermediate_reset,
game_over => intermediate_game_over,
clk25 => intermediate_clk25,
hold_out => intermediate_hold,
inverse_out => intermediate_inverse,
ballspeed_out => intermediate_ballspeed,
paddlespeed_out => intermediate_paddlespeed,
AI_out => intermediate_ai_enabled);
AI_out => intermediate_ai_enabled,
switch_out => intermediate_switch_out);

sigTime : SignalTiming port map (
hsync => intermediate_hsync,
Expand All @@ -185,7 +188,7 @@ begin
clk25 => intermediate_clk25);

bg : background port map (
switch => intermediate_keys(5), -- spacebar
switch => intermediate_switch_out, -- spacebar
X => intermediate_X,
Y => intermediate_Y,
rgb_out => intermediate_rgb1,
Expand Down

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