fixed endless loop caused by TIM2 cycle deferment

added APBDIV address to ARM package. the address is checked on memory
access after all other access attempts have failed

hardware/memory/cartridge/arm/architecture/architecture.go

@@ -91,6 +91,8 @@ type Map struct {
 	RNGSR  uint32
 	RNGDR  uint32
 
+	APBDIV uint32
+
 	// the address below which a null access is considered to have happened
 	NullAccessBoundary uint32
 
@@ -133,6 +135,8 @@ func NewMap(cart CartArchitecture) Map {
 		mmap.T1TCR = 0xe0008004
 		mmap.T1TC = 0xe0008008
 
+		mmap.APBDIV = 0xE01FC100
+
 		// boundary value is arbitrary and was suggested by John Champeau (09/04/2022)
 		mmap.NullAccessBoundary = 0x00000751
 		mmap.IllegalAccessValue = 0x00000000
@@ -164,6 +168,8 @@ func NewMap(cart CartArchitecture) Map {
 
 		mmap.FlashLatency = 10.0
 
+		// there is not MAM in this architecture but the effect of MAMfull is
+		// what we want
 		mmap.PreferredMAMCR = MAMfull
 
 		mmap.HasTIM2 = true
@@ -178,6 +184,8 @@ func NewMap(cart CartArchitecture) Map {
 		mmap.RNGSR = 0x50060804
 		mmap.RNGDR = 0x50060808
 
+		mmap.APBDIV = 0x40021004
+
 		// boundary value is arbitrary and was suggested by John Champeau (09/04/2022)
 		mmap.NullAccessBoundary = 0x00000751
 		mmap.IllegalAccessValue = 0xffffffff

hardware/memory/cartridge/arm/memory_access.go

@@ -79,6 +79,9 @@ func (arm *ARM) read8bit(addr uint32) uint8 {
 				return uint8(v)
 			}
 		}
+		if addr == arm.mmap.APBDIV {
+			return uint8(0)
+		}
 
 		arm.illegalAccess("Read 8bit", addr)
 		return uint8(arm.mmap.IllegalAccessValue)
@@ -117,6 +120,9 @@ func (arm *ARM) write8bit(addr uint32, val uint8) {
 				return
 			}
 		}
+		if addr == arm.mmap.APBDIV {
+			return
+		}
 
 		arm.illegalAccess("Write 8bit", addr)
 		return
@@ -172,6 +178,9 @@ func (arm *ARM) read16bit(addr uint32, requiresAlignment bool) uint16 {
 				return uint16(v)
 			}
 		}
+		if addr == arm.mmap.APBDIV {
+			return uint16(0)
+		}
 
 		arm.illegalAccess("Read 16bit", addr)
 		return uint16(arm.mmap.IllegalAccessValue)
@@ -224,6 +233,9 @@ func (arm *ARM) write16bit(addr uint32, val uint16, requiresAlignment bool) {
 				return
 			}
 		}
+		if addr == arm.mmap.APBDIV {
+			return
+		}
 
 		arm.illegalAccess("Write 16bit", addr)
 		return
@@ -276,6 +288,9 @@ func (arm *ARM) read32bit(addr uint32, requiresAlignment bool) uint32 {
 				return uint32(v)
 			}
 		}
+		if addr == arm.mmap.APBDIV {
+			return uint32(0)
+		}
 
 		arm.illegalAccess("Read 32bit", addr)
 		return arm.mmap.IllegalAccessValue
@@ -328,6 +343,9 @@ func (arm *ARM) write32bit(addr uint32, val uint32, requiresAlignment bool) {
 				return
 			}
 		}
+		if addr == arm.mmap.APBDIV {
+			return
+		}
 
 		arm.illegalAccess("Write 32bit", addr)
 		return

hardware/memory/cartridge/arm/peripherals/timer2.go

@@ -134,9 +134,14 @@ func (t *Timer2) ResolveDeferredCycles() {
 
 	// adjust prescaler and find number of ticks to accumulate counter by
 	var counterTicks uint32
-	for t.prescalerCounter >= t.prescalarShadow {
-		counterTicks++
-		t.prescalerCounter -= t.prescalarShadow
+	if t.prescalarShadow > 0 {
+		for t.prescalerCounter >= t.prescalarShadow {
+			counterTicks++
+			t.prescalerCounter -= t.prescalarShadow
+		}
+	} else {
+		counterTicks += t.prescalerCounter
+		t.prescalerCounter = 0
 	}
 
 	if counterTicks == 0 {