rsz: Buffering and sizing improvements #6564

openroad-ci · 2025-01-21T17:20:51Z

This PR combines a number of related resizer changes impacting QoR:

Improvements to gain buffering (repair_design -buffer_gain)
Pre-selection of buffers used for repair to filter out slow and delay buffers (except for hold repair)
Replacing resize to target slew with a fanout-of-4 rule
Restructuring of repair_design to do minimal resizing in response to a violation

It supersedes #6332

Signed-off-by: Martin Povišer <[email protected]>

povik · 2025-01-21T17:26:11Z

Dashboard link for when this PR is combined with appropriate flow script changes: https://dashboard.precisioninno.com/compare?sourceAType=Commit&sourceBType=Commit&sourceBName=3ac73fd1cbba34b80953390fc9412c84c3921133&sourceBID=16&sourceAName=c6905f5d5dab4c61d923ba4f164eb2335359cba9&sourceAID=5004

github-actions

clang-tidy made some suggestions

github-actions · 2025-01-21T17:29:04Z

src/rsz/src/RepairDesign.cc

+      }
+      size_cin /= nports;
+      if (size_cin > cin)
+        cin = size_cin;


warning: statement should be inside braces [google-readability-braces-around-statements]

Suggested change

cin = size_cin;

if (size_cin > cin) {

cin = size_cin;

}

github-actions · 2025-01-21T17:29:04Z

src/rsz/src/Resizer.cc

+  float delay_penalty = max_drive_resist * extra_input_cap;
+
+  float wlimit = maxLoad(network_->cell(worse)),
+        blimit = maxLoad(network_->cell(better));


warning: Value stored to 'blimit' during its initialization is never read [clang-analyzer-deadcode.DeadStores]

blimit = maxLoad(network_->cell(better)); ^

Additional context

src/rsz/src/Resizer.cc:539: Value stored to 'blimit' during its initialization is never read

blimit = maxLoad(network_->cell(better)); ^

github-actions · 2025-01-21T17:29:05Z

src/rsz/src/Resizer.cc

+  float delay_penalty = max_drive_resist * extra_input_cap;
+
+  float wlimit = maxLoad(network_->cell(worse)),
+        blimit = maxLoad(network_->cell(better));


warning: unused variable 'blimit' [clang-diagnostic-unused-variable]

blimit = maxLoad(network_->cell(better)); ^

github-actions · 2025-01-21T17:29:05Z

src/rsz/src/Resizer.cc

+  // TODO: factor out
+  for (TimingArcSet* arc_set : worse->timingArcSets()) {
+    TimingRole* role = arc_set->role();
+    if (role->combinational() && arc_set->from() == win


warning: static member accessed through instance [readability-static-accessed-through-instance]

Suggested change

if (role->combinational() && arc_set->from() == win

if (sta::TimingRole::combinational() && arc_set->from() == win

github-actions · 2025-01-21T17:29:05Z

src/rsz/src/Resizer.cc

+
+  for (TimingArcSet* arc_set : better->timingArcSets()) {
+    TimingRole* role = arc_set->role();
+    if (role->combinational() && arc_set->from() == bin


warning: static member accessed through instance [readability-static-accessed-through-instance]

Suggested change

if (role->combinational() && arc_set->from() == bin

if (sta::TimingRole::combinational() && arc_set->from() == bin

github-actions · 2025-01-21T17:29:05Z

src/rsz/src/Resizer.cc

+  LibertyCellSeq sizes_by_inp_cap;
+  sizes_by_inp_cap = buffer_cells_;
+  sort(sizes_by_inp_cap,
+       [this](const LibertyCell* buffer1, const LibertyCell* buffer2) {


warning: lambda capture 'this' is not used [clang-diagnostic-unused-lambda-capture]

Suggested change

[this](const LibertyCell* buffer1, const LibertyCell* buffer2) {

[](const LibertyCell* buffer1, const LibertyCell* buffer2) {

github-actions · 2025-01-21T17:29:05Z

src/rsz/src/Resizer.cc

+  while (port_iter.hasNext()) {
+    const LibertyPort* port = port_iter.next();
+    if (port->direction() == sta::PortDirection::input()) {
+      cin += port->capacitance();


warning: The left expression of the compound assignment is an uninitialized value. The computed value will also be garbage [clang-analyzer-core.uninitialized.Assign]

cin += port->capacitance(); ^

Additional context

src/rsz/src/Resizer.cc:1483: Assuming 'inst' is non-null

LibertyCell* cell = inst ? network_->libertyCell(inst) : nullptr; ^

src/rsz/src/Resizer.cc:1483: '?' condition is true

LibertyCell* cell = inst ? network_->libertyCell(inst) : nullptr; ^

src/rsz/src/Resizer.cc:1484: Assuming the condition is true

if (!network_->isTopLevelPort(drvr_pin) && inst && !dontTouch(inst) && cell ^

src/rsz/src/Resizer.cc:1484: Left side of '&&' is true

if (!network_->isTopLevelPort(drvr_pin) && inst && !dontTouch(inst) && cell ^

src/rsz/src/Resizer.cc:1484: 'inst' is non-null

if (!network_->isTopLevelPort(drvr_pin) && inst && !dontTouch(inst) && cell ^

src/rsz/src/Resizer.cc:1484: Left side of '&&' is true

if (!network_->isTopLevelPort(drvr_pin) && inst && !dontTouch(inst) && cell ^

src/rsz/src/Resizer.cc:1484: Left side of '&&' is true

if (!network_->isTopLevelPort(drvr_pin) && inst && !dontTouch(inst) && cell ^

src/rsz/src/Resizer.cc:1484: Assuming 'cell' is non-null

if (!network_->isTopLevelPort(drvr_pin) && inst && !dontTouch(inst) && cell ^

src/rsz/src/Resizer.cc:1484: Left side of '&&' is true

if (!network_->isTopLevelPort(drvr_pin) && inst && !dontTouch(inst) && cell ^

src/rsz/src/Resizer.cc:1484: Taking true branch

if (!network_->isTopLevelPort(drvr_pin) && inst && !dontTouch(inst) && cell ^

src/rsz/src/Resizer.cc:1486: 'cin' declared without an initial value

float cin, load_cap; ^

src/rsz/src/Resizer.cc:1491: Assuming the condition is true

if (load_cap > 0.0 && getCin(cell, cin)) { ^

src/rsz/src/Resizer.cc:1491: Left side of '&&' is true

if (load_cap > 0.0 && getCin(cell, cin)) { ^

src/rsz/src/Resizer.cc:1491: Passing value via 2nd parameter 'cin'

if (load_cap > 0.0 && getCin(cell, cin)) { ^

src/rsz/src/Resizer.cc:1491: Calling 'Resizer::getCin'

if (load_cap > 0.0 && getCin(cell, cin)) { ^

src/rsz/src/Resizer.cc:1465: Loop condition is true. Entering loop body

while (port_iter.hasNext()) { ^

src/rsz/src/Resizer.cc:1467: Assuming the condition is true

if (port->direction() == sta::PortDirection::input()) { ^

src/rsz/src/Resizer.cc:1467: Taking true branch

if (port->direction() == sta::PortDirection::input()) { ^

src/rsz/src/Resizer.cc:1468: The left expression of the compound assignment is an uninitialized value. The computed value will also be garbage

cin += port->capacitance(); ^

github-actions · 2025-01-21T17:29:05Z

src/rsz/src/Resizer.cc

+    // Includes net parasitic capacitance.
+    load_cap = graph_delay_calc_->loadCap(drvr_pin, tgt_slew_dcalc_ap_);
+    if (load_cap > 0.0 && getCin(cell, cin)) {
+      bool is_buf_inv = cell->isBuffer() || cell->isInverter();


warning: Value stored to 'is_buf_inv' during its initialization is never read [clang-analyzer-deadcode.DeadStores]

bool is_buf_inv = cell->isBuffer() || cell->isInverter(); ^

Additional context

src/rsz/src/Resizer.cc:1492: Value stored to 'is_buf_inv' during its initialization is never read

bool is_buf_inv = cell->isBuffer() || cell->isInverter(); ^

github-actions · 2025-01-21T17:29:05Z

src/rsz/src/Resizer.cc

+    // Includes net parasitic capacitance.
+    load_cap = graph_delay_calc_->loadCap(drvr_pin, tgt_slew_dcalc_ap_);
+    if (load_cap > 0.0 && getCin(cell, cin)) {
+      bool is_buf_inv = cell->isBuffer() || cell->isInverter();


warning: unused variable 'is_buf_inv' [clang-diagnostic-unused-variable]

bool is_buf_inv = cell->isBuffer() || cell->isInverter(); ^

maliberty · 2025-01-21T20:08:43Z

src/rsz/test/buffer_varying_lengths.ok

+Differences found at line 95.
+    - i1-179 BUF_X16 + PLACED ( 0 3580000 ) N ;
+    - i1-179 BUF_X8 + PLACED ( 0 3580000 ) N ;


There should be no diffs in the ok file

Ah, missed that, will fix here and in other places if there are any

maliberty · 2025-01-21T20:09:55Z

src/rsz/src/Resizer.cc

+#if 0
+  if (/* blimit exists */ blimit > 0 && wlimit > blimit) {
+    return false;
+  }
+#endif


rm unused code

maliberty · 2025-01-22T05:40:15Z

09:38:53  The following tests FAILED:
09:38:53  	366 - gpl.convergence01.tcl (Failed)
09:38:53  	367 - gpl.convergence01.py (Failed)
09:38:53  	389 - gpl.simple01-td.tcl (Failed)
09:38:53  	390 - gpl.simple01-td.py (Failed)
09:38:53  	391 - gpl.simple01-td-tune.tcl (Failed)
09:38:53  	392 - gpl.simple01-td-tune.py (Failed)

needs attention

Signed-off-by: Martin Povišer <[email protected]>

…nges

Signed-off-by: Martin Povišer <[email protected]>

github-actions · 2025-01-23T13:28:00Z

clang-tidy review says "All clean, LGTM! 👍"

Signed-off-by: Martin Povišer <[email protected]>

github-actions · 2025-01-23T15:00:45Z

clang-tidy review says "All clean, LGTM! 👍"

povik · 2025-01-28T09:47:27Z

Updated dashboard results: https://dashboard.precisioninno.com/compare?sourceAType=Commit&sourceBType=Commit&sourceName=23eb6ca160e7d660d18527060f4f4d82bdda161a&sourceAName=09ec72a7354c364b458c5c1b63bbaaad9bbd08c3&sourceAID=5061&sourceBName=23eb6ca160e7d660d18527060f4f4d82bdda161a&sourceBID=20

Signed-off-by: Martin Povišer <[email protected]>

github-actions · 2025-01-28T17:25:25Z

clang-tidy review says "All clean, LGTM! 👍"

precisionmoon · 2025-01-29T00:57:55Z

Updated dashboard results: https://dashboard.precisioninno.com/compare?sourceAType=Commit&sourceBType=Commit&sourceName=23eb6ca160e7d660d18527060f4f4d82bdda161a&sourceAName=09ec72a7354c364b458c5c1b63bbaaad9bbd08c3&sourceAID=5061&sourceBName=23eb6ca160e7d660d18527060f4f4d82bdda161a&sourceBID=20

Overall timing QoR looks quite good. Average setup TNS improved by 9.4% and setup TNS by 6.5%. I looked at 5 worst degradations. The QoR degradation starts at GR or DR. Details are below.

https://docs.google.com/spreadsheets/d/1IhTu-hxiFy9czpuv0bu-kM2QFB11Hj0M/edit?usp=drive_link&ouid=104723144681287518905&rtpof=true&sd=true

maliberty · 2025-02-13T21:11:53Z

Please resolve the merge conflicts so we can get this in.

povik added 14 commits January 21, 2025 17:43

rsz: Factor out areCellsSwappable

7422734

Signed-off-by: Martin Povišer <[email protected]>

rsz: Decouple resize to target slew from violation repair

7868c5c

Signed-off-by: Martin Povišer <[email protected]>

rsz: Fix tidy warnings

ae6e4d8

Signed-off-by: Martin Povišer <[email protected]>

rsz: Account for margin in driver slew repair

cb30344

Signed-off-by: Martin Povišer <[email protected]>

rsz: Pre-select buffers for gain buffering

e18f9b9

Signed-off-by: Martin Povišer <[email protected]>

rsz: Use pre-selected buffers for rebuffering too

6902eda

Signed-off-by: Martin Povišer <[email protected]>

rsz: Use fo4 on largest gate size to decide buffering need

1256f39

Signed-off-by: Martin Povišer <[email protected]>

rsz: Apply gain-buffering to top inputs too

6eea2d0

Signed-off-by: Martin Povišer <[email protected]>

rsz: Move to 'cap ratio' sizing and fix buffering

dad1cd4

Signed-off-by: Martin Povišer <[email protected]>

rsz: Move early sizing up front in repair_design

7e396b4

Signed-off-by: Martin Povišer <[email protected]>

rsz: Size buffers using higher cap ratio

6f2afb7

Signed-off-by: Martin Povišer <[email protected]>

rsz: Format

d3c137c

Signed-off-by: Martin Povišer <[email protected]>

rsz: Update tests

287d290

Signed-off-by: Martin Povišer <[email protected]>

rsz: Rm commented-out target slew calls

5a18cf3

Signed-off-by: Martin Povišer <[email protected]>

openroad-ci assigned povik Jan 21, 2025

povik requested review from precisionmoon and maliberty January 21, 2025 17:21

povik mentioned this pull request Jan 21, 2025

Resize to target slew removal 1 #6332

Closed

github-actions bot reviewed Jan 21, 2025

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maliberty reviewed Jan 21, 2025

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povik added 4 commits January 23, 2025 13:28

rsz: Tidy

f947840

Signed-off-by: Martin Povišer <[email protected]>

rsz: Update tests

1b42e5e

Signed-off-by: Martin Povišer <[email protected]>

Merge remote-tracking branch 'origin/master' into rsz-gain-buffer-cha…

a36b2c3

…nges

gpl: Update tests for resizer changes

a119c47

Signed-off-by: Martin Povišer <[email protected]>

rsz: Add 'report_fast_buffer_sizes' debugging command

bc21f9d

Signed-off-by: Martin Povišer <[email protected]>

gpl: Update test for resizer change

02fa259

Signed-off-by: Martin Povišer <[email protected]>

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rsz: Buffering and sizing improvements #6564

rsz: Buffering and sizing improvements #6564

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edited

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maliberty commented Feb 13, 2025

	if (role->combinational() && arc_set->from() == win
	if (sta::TimingRole::combinational() && arc_set->from() == win

	[this](const LibertyCell* buffer1, const LibertyCell* buffer2) {
	[](const LibertyCell* buffer1, const LibertyCell* buffer2) {

rsz: Buffering and sizing improvements #6564

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