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verilog_instance.vim: create instantiation of ports from port declaration

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verilog-instance.vim

Create SystemVerilog port instantiation from port declaration.

Work on modules, tasks, functions and all other similar structures.

Installation

Use your favorite plugin manager.

Using vim-plug:

Plug 'antoinemadec/vim-verilog-instance'

Quick start guide

try these commands:

  • gbi(
    • Start VerilogInstance command (gb) for inner (parenthesis
  • vjjgb
    • visual-select j down twice
    • Start VerilogInstance command (gb) on the 3 selected lines

Options

  • let g:verilog_instance_skip_last_coma = {0/1}
    • When the variable is 1, last printed line will skip the coma. Default value is 0.
  • let g:verilog_instance_keep_comments = {0/1}
    • When the variable is 1, comments will be kept (block comments /* */ not support!). Default value is 0.
  • let g:verilog_instance_keep_empty_lines = {0/1}
    • When the variable is 1, empty lines in your code will be printed. Default value is 0.

Other vim plugins for Verilog/SystemVerilog

verilog_systemverilog

verilog_systemverilog is a syntax plugin for Verilog and SystemVerilog

Author

Antoine Madec

License

MIT

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verilog_instance.vim: create instantiation of ports from port declaration

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