Create SystemVerilog port instantiation from port declaration.
Work on modules, tasks, functions and all other similar structures.
Use your favorite plugin manager.
Using vim-plug:
Plug 'antoinemadec/vim-verilog-instance'
try these commands:
gbi(
- Start VerilogInstance command (
gb
) fori
nner(
parenthesis
- Start VerilogInstance command (
vjjgb
v
isual-selectj
down twice- Start VerilogInstance command (
gb
) on the 3 selected lines
- let g:verilog_instance_skip_last_coma = {0/1}
- When the variable is 1, last printed line will skip the coma. Default value is 0.
- let g:verilog_instance_keep_comments = {0/1}
- When the variable is 1, comments will be kept (block comments /* */ not support!). Default value is 0.
- let g:verilog_instance_keep_empty_lines = {0/1}
- When the variable is 1, empty lines in your code will be printed. Default value is 0.
verilog_systemverilog is a syntax plugin for Verilog and SystemVerilog
MIT