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arch/arm/max326xx: add max32690 icc updates
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Add updates for MAX32690 Instruction Cache Controller to enhance device support in NuttX architecture.
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lordrasmus authored and acassis committed Feb 11, 2025
1 parent e99c516 commit 381d3fe
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Showing 4 changed files with 151 additions and 7 deletions.
7 changes: 6 additions & 1 deletion arch/arm/src/max326xx/Make.defs
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Expand Up @@ -29,7 +29,12 @@ include armv7-m/Make.defs
CHIP_CSRCS = max326_start.c max326_irq.c max326_clrpend.c

ifeq ($(CONFIG_MAX326XX_ICC),y)
CHIP_CSRCS += max326_icc.c
ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
CHIP_CSRCS += max32660_icc.c
endif
ifeq ($(CONFIG_ARCH_FAMILY_MAX32690),y)
CHIP_CSRCS += max32690_icc.c
endif
endif

ifeq ($(CONFIG_RTC_DRIVER),y)
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18 changes: 14 additions & 4 deletions arch/arm/src/max326xx/hardware/max326_icc.h
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Expand Up @@ -43,10 +43,20 @@

/* Register Addresses *******************************************************/

#define MAX326_ICC_ID (MAX326_ICC_BASE + MAX326_ICC_ID_OFFSET)
#define MAX326_ICC_MEMCFG (MAX326_ICC_BASE + MAX326_ICC_MEMCFG_OFFSET)
#define MAX326_ICC_CTRLSTAT (MAX326_ICC_BASE + MAX326_ICC_CTRLSTAT_OFFSET)
#define MAX326_ICC_INVDTALL (MAX326_ICC_BASE + MAX326_ICC_INVDTALL_OFFSET)
/* The MAX32690 has two ICC controllers because it includes a
* second integrated RISC-V core.
*/
#if defined(CONFIG_ARCH_FAMILY_MAX32690)
#define MAX326_ICC0_ID (MAX326_ICC0_BASE + MAX326_ICC_ID_OFFSET)
#define MAX326_ICC0_MEMCFG (MAX326_ICC0_BASE + MAX326_ICC_MEMCFG_OFFSET)
#define MAX326_ICC0_CTRLSTAT (MAX326_ICC0_BASE + MAX326_ICC_CTRLSTAT_OFFSET)
#define MAX326_ICC0_INVDTALL (MAX326_ICC0_BASE + MAX326_ICC_INVDTALL_OFFSET)
#else
#define MAX326_ICC_ID (MAX326_ICC_BASE + MAX326_ICC_ID_OFFSET)
#define MAX326_ICC_MEMCFG (MAX326_ICC_BASE + MAX326_ICC_MEMCFG_OFFSET)
#define MAX326_ICC_CTRLSTAT (MAX326_ICC_BASE + MAX326_ICC_CTRLSTAT_OFFSET)
#define MAX326_ICC_INVDTALL (MAX326_ICC_BASE + MAX326_ICC_INVDTALL_OFFSET)
#endif

/* Register Bit-field Definitions *******************************************/

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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/max326xx/common/max326_icc.c
* arch/arm/src/max326xx/max32660/max32660_icc.c
*
* SPDX-License-Identifier: Apache-2.0
*
Expand Down Expand Up @@ -57,11 +57,13 @@ void max326_icc_enable(bool enable)

max326_icc_enableclk();

putreg32(1, MAX326_ICC_INVDTALL);

/* Enable the cache and wait for it to become ready */

putreg32(ICC_CTRLSTAT_ENABLE, MAX326_ICC_CTRLSTAT);
do
{
putreg32(ICC_CTRLSTAT_ENABLE, MAX326_ICC_CTRLSTAT);
regval = getreg32(MAX326_ICC_CTRLSTAT);
}
while ((regval & ICC_CTRLSTAT_READY) == 0);
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127 changes: 127 additions & 0 deletions arch/arm/src/max326xx/max32690/max32690_icc.c
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@@ -0,0 +1,127 @@
/****************************************************************************
* arch/arm/src/max326xx/max32690/max32690_icc.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/

/****************************************************************************
* Included Files
****************************************************************************/

#include <nuttx/config.h>

#include <stdint.h>
#include <stdbool.h>
#include <assert.h>

#include "arm_internal.h"
#include "hardware/max326_icc.h"
#include "max326_periphclks.h"
#include "max326_icc.h"

/****************************************************************************
* Public Functions
****************************************************************************/

/****************************************************************************
* Name: max326_icc_enable
*
* Description:
* Enables or disables the instruction cache.
* The MAX32690 actually has two cache controllers.
* Support for the RISC-V core will be added later.
*
****************************************************************************/

void max326_icc_enable(bool enable)
{
uint32_t regval;

if (enable)
{
/* Enable ICC peripheral clocking */

max326_syscache_enableclk();

putreg32(1, MAX326_ICC0_INVDTALL);

/* Enable the cache and wait for it to become ready */

putreg32(ICC_CTRLSTAT_ENABLE, MAX326_ICC0_CTRLSTAT);
do
{
regval = getreg32(MAX326_ICC0_CTRLSTAT);
}
while ((regval & ICC_CTRLSTAT_READY) == 0);
}
else
{
/* Disable the cache */

putreg32(0, MAX326_ICC0_CTRLSTAT);

/* Disable clocking to the ICC peripheral */

max326_syscache_disableclk();
}
}

/****************************************************************************
* Name: max326_icc_invalidate
*
* Description:
* Invalidate the instruction cache
*
****************************************************************************/

void max326_icc_invalidate(void)
{
/* Any write to the INVDTALL register will invalidate the entire cache. */

putreg32(1, MAX326_ICC0_INVDTALL);

/* Wait for the cache to become ready again */

while ((getreg32(MAX326_ICC0_CTRLSTAT) & ICC_CTRLSTAT_READY) == 0)
{
}
}

/****************************************************************************
* Name: up_addrenv_coherent
*
* Description:
* Flush D-Cache and invalidate I-Cache in preparation for a change in
* address environments. This should immediately precede a call to
* up_addrenv_select();
*
* Input Parameters:
* addrenv - Describes the address environment to be made coherent.
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/

#ifdef CONFIG_ARCH_ADDRENV
int up_addrenv_coherent(const arch_addrenv_t *addrenv)
{
max326_icc_invalidate();
}
#endif

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