Mainly style fixes.

Minor fixes

.github/pull_request_template.md

@@ -1,8 +1,11 @@
 # New Features
+
 * tbd
 
 # Changes
+
 * tbd
 
 # Bug Fixes
+
 * tbd

README.md

@@ -47,13 +47,15 @@ such a model, while supporting multiple input sources.
   * top-down (project → design → fileset → file) or
   * bottom-up (file → fileset → design → project) or
   * parsing a project file.
+
 * Designs, filesets and files can use absolute or relative paths.
   * `ResolvedPath` returns the resolved absolute path to an object.
+
 * Projects, designs, filesets and files can be validated (e.g. if the path exists).
+
 * Projects, designs, filesets and files can have user-defined attributes.
   * User-defined attributes are resolved bottom-up.
 
-
 # Project File Readers
 
 ## OSVVM `*.pro` File Reader
@@ -67,10 +69,10 @@ ProjectModel can read `*.xpr` files and extract source, constraint and simulatio
 files while preserving the fileset structure.
 
 # Use Cases
+
 * Reading OSVVM's `*.pro` files.
 * Reading Xilinx Vivado's `*.xpr` files.
 
-
 # Examples
 
 ```python
@@ -96,19 +98,16 @@ for file in designA.Files(fileType=VHDLSourceFile):
 	print(f"  {file.Path}")
 ```
 
-
 # References
 
-- [Paebbels/pyIPCMI: pyIPCMI/Base/Project.py](https://GitHub.com/Paebbels/pyIPCMI/blob/master/pyIPCMI/Base/Project.py)
-- [VUnit/vunit: vunit/project.py](https://GitHub.com/VUnit/vunit/blob/master/vunit/project.py)
-- [PyFPGA/pyfpga: fpga/project.py](https://GitHub.com/PyFPGA/pyfpga/blob/main/fpga/project.py)
-- [olofk/fusesoc: fusesoc/capi2/core.py](https://GitHub.com/olofk/fusesoc/blob/master/fusesoc/capi2/core.py)
-- [XedaHQ/xeda: xeda/flows/flow.py](https://GitHub.com/XedaHQ/xeda/blob/master/xeda/flows/flow.py)
-- [tsfpga/tsfpga: tsfpga/build_project_list.py](https://gitlab.com/tsfpga/tsfpga/-/blob/master/tsfpga/build_project_list.py)
-- [hdl-make: hdlmake/](https://ohwr.org/project/hdl-make/tree/master/hdlmake)
-- [OSVVM/OSVVM-Scripts: OsvvmProjectScripts.tcl](https://GitHub.com/OSVVM/OSVVM-Scripts/blob/master/OsvvmProjectScripts.tcl)
-
-
+* [Paebbels/pyIPCMI: pyIPCMI/Base/Project.py](https://GitHub.com/Paebbels/pyIPCMI/blob/master/pyIPCMI/Base/Project.py)
+* [VUnit/vunit: vunit/project.py](https://GitHub.com/VUnit/vunit/blob/master/vunit/project.py)
+* [PyFPGA/pyfpga: fpga/project.py](https://GitHub.com/PyFPGA/pyfpga/blob/main/fpga/project.py)
+* [olofk/fusesoc: fusesoc/capi2/core.py](https://GitHub.com/olofk/fusesoc/blob/master/fusesoc/capi2/core.py)
+* [XedaHQ/xeda: xeda/flows/flow.py](https://GitHub.com/XedaHQ/xeda/blob/master/xeda/flows/flow.py)
+* [tsfpga/tsfpga: tsfpga/build_project_list.py](https://gitlab.com/tsfpga/tsfpga/-/blob/master/tsfpga/build_project_list.py)
+* [hdl-make: hdlmake/](https://ohwr.org/project/hdl-make/tree/master/hdlmake)
+* [OSVVM/OSVVM-Scripts: OsvvmProjectScripts.tcl](https://GitHub.com/OSVVM/OSVVM-Scripts/blob/master/OsvvmProjectScripts.tcl)
 
 # Contributors
 
@@ -117,7 +116,6 @@ for file in designA.Files(fileType=VHDLSourceFile):
 * [Stefan Unrein](https://GitHub.com/stefanunrein)
 * [and more...](https://GitHub.com/edaa-org/pyEDAA.ProjectModel/graphs/contributors)
 
-
 # License
 
 This Python package (source code) licensed under [Apache License 2.0](LICENSE.md).  

pyEDAA/ProjectModel/OSVVM.py

@@ -29,7 +29,6 @@
 # SPDX-License-Identifier: Apache-2.0
 # ============================================================================
 #
-from enum import Enum, unique
 from pathlib import Path
 
 from pyTooling.Decorators import export

pyEDAA/ProjectModel/__init__.py

@@ -255,7 +255,6 @@ def __getitem__(self, key: Type[Attribute]):
 
 	def __setitem__(self, key: Type[Attribute], value: typing_Any):
 		"""Index access for setting attributes on this file."""
-		x = key.VALUE_TYPE
 		self._attributes[key] = value
 
 

tests/VivadoProject/StopWatch/README.md

@@ -2,8 +2,6 @@
 
 The VHDL StopWatch Vivado project is the solution to the **Professional VHDL** 5-days class offered by PLC2.
 
-
-
 # License
 
 Licensed under [MIT License](LICENSE.md).