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Changes due to default branch name 'main'.
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Paebbels committed Sep 25, 2021
1 parent 8837f37 commit 0394692
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2 changes: 1 addition & 1 deletion doc/Dependency.rst
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Expand Up @@ -10,7 +10,7 @@ Dependency
.. |img-pySVModel-req-status| image:: https://img.shields.io/requires/github/edaa-org/pySystemVerilogModel
:alt: Requires.io
:height: 22
:target: https://requires.io/github/edaa-org/pySystemVerilogModel/requirements/?branch=master
:target: https://requires.io/github/edaa-org/pySystemVerilogModel/requirements/?branch=main

+------------------------------------------+------------------------------------------+
| `Libraries.io <https://libraries.io/>`_ | `Requires.io <https://requires.io/>`_ |
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4 changes: 2 additions & 2 deletions doc/conf.py
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Expand Up @@ -224,8 +224,8 @@ def _LatestTagName():
extlinks = {
'issue': ('https://github.com/edaa-org/pySystemVerilogModel/issues/%s', 'issue #'),
'pull': ('https://github.com/edaa-org/pySystemVerilogModel/pull/%s', 'pull request #'),
'src': ('https://github.com/edaa-org/pySystemVerilogModel/blob/master/pySystemVerilogModel/%s?ts=2', None),
# 'test': ('https://github.com/edaa-org/pySystemVerilogModel/blob/master/test/%s?ts=2', None)
'src': ('https://github.com/edaa-org/pySystemVerilogModel/blob/main/pySystemVerilogModel/%s?ts=2', None),
# 'test': ('https://github.com/edaa-org/pySystemVerilogModel/blob/main/test/%s?ts=2', None)
}


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