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@@ -1,2 +1,2 @@ | ||
wheel>=0.38.1 | ||
twine | ||
wheel >= 0.40.0 | ||
twine >= 4.0.2 |
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@@ -11,7 +11,7 @@ | |
# # | ||
# License: # | ||
# ==================================================================================================================== # | ||
# Copyright 2021-2022 Patrick Lehmann - Boetzingen, Germany # | ||
# Copyright 2021-2023 Patrick Lehmann - Boetzingen, Germany # | ||
# # | ||
# Licensed under the Apache License, Version 2.0 (the "License"); # | ||
# you may not use this file except in compliance with the License. # | ||
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@@ -31,7 +31,7 @@ | |
""" | ||
An abstract SystemVerilog language model. | ||
:copyright: Copyright 2021-2022 Patrick Lehmann - Bötzingen, Germany | ||
:copyright: Copyright 2021-2023 Patrick Lehmann - Bötzingen, Germany | ||
:license: Apache License, Version 2.0 | ||
""" | ||
from enum import unique, Enum | ||
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__author__ = "Patrick Lehmann" | ||
__email__ = "[email protected]" | ||
__copyright__ = "2021-2022, Patrick Lehmann" | ||
__copyright__ = "2021-2023, Patrick Lehmann" | ||
__license__ = "Apache License, Version 2.0" | ||
__version__ = "0.3.6" | ||
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@@ -8,5 +8,5 @@ pytest>=7.2.0 | |
pytest-cov>=4.0.0 | ||
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# Static Type Checking | ||
mypy>=0.990 | ||
mypy >= 1.2 | ||
lxml>=4.9 |
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