v0.2.0

.btd.yml

@@ -4,6 +4,6 @@ requirements: requirements.txt
 target: gh-pages
 formats: [ html, pdf, man ]
 images:
-  base: vhdl/doc
+  base: edaa/doc
   latex: btdi/latex
 theme: https://codeload.github.com/buildthedocs/sphinx.theme/tar.gz/v1

.github/workflows/Pipeline.yml

@@ -310,14 +310,14 @@ jobs:
       - name: Checkout repository
         uses: actions/checkout@v2
 
-      - name: 🚢 Build container image 'vhdl/doc'
+      - name: 🚢 Build container image 'EDAA/doc'
         run: |
-          docker build -t vhdl/doc - <<-EOF
+          docker build -t edaa/doc - <<-EOF
           FROM btdi/sphinx:featured
           RUN apk add -U --no-cache graphviz
           EOF
 
-      - name: 🛳️ Build documentation from './pySystemVerilogModel/doc' and publish to GitHub Pages
+      - name: 🛳️ Build documentation using container edaa/doc and publish to GitHub Pages
         uses: buildthedocs/btd@v0
         with:
           token: ${{ github.token }}

.gitignore

@@ -14,8 +14,8 @@ coverage.xml
 
 # Sphinx
 doc/_build/
-doc/pyVHDLModel/**/*.*
-!doc/pyVHDLModel/index.rst
+doc/pySystemVerilogModel/**/*.*
+!doc/pySystemVerilogModel/index.rst
 
 # BuildTheDocs
 doc/_theme/**/*.*

README.md

@@ -32,8 +32,8 @@ This package provides a unified abstract language model for SystemVerilog (incl.
 Projects reading from source files can derive own classes and implement additional logic to create a concrete language
 model for their tools.
 
-Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services
-on such a model, while supporting multiple frontends.
+Projects consuming pre-processed System Verilog data (parsed, analyzed or elaborated) can build higher level features
+and services on such a model, while supporting multiple frontends.
 
 
 ## Use Cases
@@ -46,20 +46,17 @@ on such a model, while supporting multiple frontends.
 
 *TBD*
 
-
 ## Examples
 
 ### List all Modules with Parameters and Ports
 
-* TBD
-
+*TBD*
 
 ## Contributors
 
 * [Patrick Lehmann](https://github.com/Paebbels) (Maintainer)
 * [Unai Martinez-Corral](https://github.com/umarcor)
-* [and more...](https://github.com/VHDL/pySystemVerilogModel/graphs/contributors)
-
+* [and more...](https://github.com/edaa-org/pySystemVerilogModel/graphs/contributors)
 
 ## License
 

doc/LanguageModel/index.rst

@@ -1,14 +1,14 @@
-.. _vhdlmodel:
+.. _svmodel:
 
 SystemVerilog Language Model
 ############################
 
 .. topic:: Design Goal
 
-   * Clearly named classes that model the semantics of VHDL.
-   * All language constructs (statements, declarations, specifications, …) have
-     their own classes. |br| These classes are arranged in a logical hierarchy,
-     with a single common base-class.
+   * Clearly named classes that model the semantics of System Verilog.
+   * All language constructs (statements, declarations, specifications, …) have their own classes.
+     |br|
+     These classes are arranged in a logical hierarchy, with a single common base-class.
    * Child objects shall have a reference to their parent.
    * Comments will be associated with a particular code object.
    * Easy modifications of the object tree.

doc/conf.py

@@ -36,8 +36,8 @@ def _LatestTagName():
 	return check_output(["git", "describe", "--abbrev=0", "--tags"], universal_newlines=True).strip()
 
 # The full version, including alpha/beta/rc tags
-version = "0.1"     # The short X.Y version.
-release = "0.1.2"   # The full version, including alpha/beta/rc tags.
+version = "0.2"     # The short X.Y version.
+release = "0.2.0"   # The full version, including alpha/beta/rc tags.
 try:
 	if _IsUnderGitControl:
 		latestTagName = _LatestTagName()[1:]		# remove prefix "v"
@@ -111,7 +111,7 @@ def _LatestTagName():
 html_favicon = str(Path(html_static_path[0]) / "favicon.svg")
 
 # Output file base name for HTML help builder.
-htmlhelp_basename = 'pyVHDLModelDoc'
+htmlhelp_basename = 'pySystemVerilogModelDoc'
 
 # If not None, a 'Last updated on:' timestamp is inserted at every page
 # bottom, using the given strftime format.

doc/index.rst

@@ -23,23 +23,20 @@
 The pySystemVerilogModel Documentation
 ######################################
 
-An abstract SystemVerilog language model.
-
+An abstract System Verilog language model.
 
 
 .. _goals:
 
 Main Goals
 **********
 
-This package provides a unified abstract language model for SystemVerilog (incl.
-Verilog). Projects reading from source files can derive own classes and implement
-additional logic to create a concrete language model for their tools.
-
-Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can
-build higher level features and services on such a model, while supporting multiple
-frontends.
+This package provides a unified abstract language model for System Verilog (incl. Verilog).
+Projects reading from source files can derive own classes and implement additional logic to create a concrete language
+model for their tools.
 
+Projects consuming pre-processed System Verilog data (parsed, analyzed or elaborated) can build higher level features
+and services on such a model, while supporting multiple frontends.
 
 
 .. _usecase:
@@ -65,8 +62,7 @@ News
 
    .. rubric:: New Repository Created
 
-* Moved ``VerilogVersion`` and ``SystemVerilogVersion`` classes from ``pyEDAA.ProjectModel``
-  to this new repository.
+* Moved ``VerilogVersion`` and ``SystemVerilogVersion`` classes from ``pyEDAA.ProjectModel`` to this new repository.
 
 
 .. _contributors:
@@ -76,7 +72,7 @@ Contributors
 
 * `Patrick Lehmann <https://github.com/Paebbels>`__ (Maintainer)
 * `Unai Martinez-Corral <https://github.com/umarcor/>`__
-* `and more... <https://github.com/edaa-org/pyVHDLModel/graphs/contributors>`__
+* `and more... <https://github.com/edaa-org/pySystemVerilogModel/graphs/contributors>`__
 
 
 License

doc/pySystemVerilogModel/index.rst

@@ -1,3 +1,3 @@
 .. toctree::
 
-   pyVHDLModel
+   pySystemVerilogModel

pySystemVerilogModel/__init__.py

@@ -45,29 +45,29 @@
 from pydecor  import export
 
 
-__version__ = "0.1.2"
+__version__ = "0.2.0"
 
 
 @export
 @unique
 class VerilogVersion(Enum):
-	VHDL95 =             95
-	VHDL2001 =         2001
-	VHDL2005 =         2005
+	Verilog95 =             95
+	Verilog2001 =         2001
+	Verilog2005 =         2005
 
 	__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
-		95:     VHDL95,
-		1:      VHDL2001,
-		5:      VHDL2005,
-		1995:   VHDL95,
-		2001:   VHDL2001,
-		2005:   VHDL2005,
-		"95":   VHDL95,
-		"01":   VHDL2001,
-		"05":   VHDL2005,
-		"1995": VHDL95,
-		"2001": VHDL2001,
-		"2005": VHDL2005,
+		95:     Verilog95,
+		1:      Verilog2001,
+		5:      Verilog2005,
+		1995:   Verilog95,
+		2001:   Verilog2001,
+		2005:   Verilog2005,
+		"95":   Verilog95,
+		"01":   Verilog2001,
+		"05":   Verilog2005,
+		"1995": Verilog95,
+		"2001": Verilog2001,
+		"2005": Verilog2005,
 	}
 
 	def __init__(self, *_):
@@ -114,28 +114,28 @@ def __repr__(self):
 @export
 @unique
 class SystemVerilogVersion(Enum):
-	VHDL2005 =         2005
-	VHDL2009 =         2009
-	VHDL2012 =         2012
-	VHDL2017 =         2017
+	SystemVerilog2005 =         2005
+	SystemVerilog2009 =         2009
+	SystemVerilog2012 =         2012
+	SystemVerilog2017 =         2017
 
 	__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
-		5:      VHDL2005,
-		9:      VHDL2009,
-		12:     VHDL2012,
-		17:     VHDL2017,
-		2005:   VHDL2005,
-		2009:   VHDL2009,
-		2012:   VHDL2012,
-		2017:   VHDL2017,
-		"05":   VHDL2005,
-		"09":   VHDL2009,
-		"12":   VHDL2012,
-		"17":   VHDL2017,
-		"2005": VHDL2005,
-		"2009": VHDL2009,
-		"2012": VHDL2012,
-		"2017": VHDL2017,
+		5:      SystemVerilog2005,
+		9:      SystemVerilog2009,
+		12:     SystemVerilog2012,
+		17:     SystemVerilog2017,
+		2005:   SystemVerilog2005,
+		2009:   SystemVerilog2009,
+		2012:   SystemVerilog2012,
+		2017:   SystemVerilog2017,
+		"05":   SystemVerilog2005,
+		"09":   SystemVerilog2009,
+		"12":   SystemVerilog2012,
+		"17":   SystemVerilog2017,
+		"2005": SystemVerilog2005,
+		"2009": SystemVerilog2009,
+		"2012": SystemVerilog2012,
+		"2017": SystemVerilog2017,
 	}
 
 	def __init__(self, *_):

setup.py

@@ -8,7 +8,7 @@
 # ==============================================================================
 # Authors:            Patrick Lehmann
 #
-# Package installer:  An abstract VHDL language model.
+# Package installer:  An abstract System Verilog language model.
 #
 # License:
 # ============================================================================
@@ -32,7 +32,7 @@
 from pathlib    import Path
 from setuptools import setup as setuptools_setup, find_packages as setuptools_find_packages
 
-gitHubNamespace = "vhdl"
+gitHubNamespace = "edaa-org"
 projectName =     "pySystemVerilogModel"
 
 # Read README for upload to PyPI
@@ -52,7 +52,7 @@
 # Assemble all package information
 setuptools_setup(
 	name=projectName,
-	version="0.1.2",
+	version="0.2.0",
 
 	author="Patrick Lehmann",
 	author_email="[email protected]",
@@ -70,7 +70,7 @@
 		'Source Code':   sourceCodeURL,
 		'Issue Tracker': sourceCodeURL + "/issues"
 	},
-	# download_url="https://github.com/vhdl/pyVHDLModel/tarball/0.1.0",
+	# download_url="https://github.com/edaa-org/pySystemVerilogModel/tarball/0.1.0",
 
 	packages=setuptools_find_packages(exclude=["tests", "tests.*",]),
 	classifiers=[