v0.2.2

Release created on: 04.10.2021 - 00:11:34

Changes

• Renamed project from pySystemVerilogModel to pySVModel.
• Updated requirements to Coverage.py 6.0 and Sphinx 4.2

v0.2.1

Release created on: 29.09.2021 - 14:16:51

Bug Fixes

• Added missing Any values for VerilogVersion and SystemVerilogversion.

v0.2.0

Release created on: 28.09.2021 - 21:28:49

Changes

• Updated documentation after initial copy&paste from pyVHDLModel.

Bug Fixes

• Fixed copy&paste errors like:
  • VHDL → Verilog / SystemVerilog

v0.1.2

Release created on: 25.09.2021 - 20:31:26

New Features

• Build documentation with BTD.

Changes

• tbd

Bug Fixes

• Fixed URLs due to default branch name main.

v0.1.1

Bumped version to v0.1.1.

v0.1.0

Release created on: 25.09.2021 - 17:45:02

New Features

• Moved classes VerilogVersion and SystemVerilogVersion from pyEDAA.ProjectModel to this package.