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Add RP references with first letter of register name
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eliben committed Jul 16, 2020
1 parent 8969fb4 commit b6d61a3
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Showing 2 changed files with 22 additions and 9 deletions.
10 changes: 4 additions & 6 deletions src/assembler.js
Original file line number Diff line number Diff line change
Expand Up @@ -411,12 +411,10 @@ class Assembler {
// Expect arg to be a register pair and return its encoding.
_argRP(sl, arg) {
switch (arg.toLowerCase()) {
case 'bc': return 0b00;
case 'de': return 0b01;
case 'hl': return 0b10;
case 'sp':
case 'psw':
return 0b11;
case 'bc': case 'b': return 0b00;
case 'de': case 'd': return 0b01;
case 'hl': case 'h': return 0b10;
case 'sp': case 'psw': return 0b11;
default:
this._assemblyError(sl.pos, `invalid register pair ${arg}`);
}
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21 changes: 18 additions & 3 deletions test/test.js
Original file line number Diff line number Diff line change
Expand Up @@ -487,6 +487,24 @@ There: mvi a, 30
assert.equal(state.e, 0x34);
});

it('rp-single-char-ref', () => {
// Test that referring to register pairs by the name of the first register
// in the pair works OK.
let [state, mem] = runProg(`
lxi h, 1234h
lxi d, 4567h
lxi b, abcdh
hlt
`);
assert.ok(state.halted);
assert.equal(state.h, 0x12);
assert.equal(state.l, 0x34);
assert.equal(state.d, 0x45);
assert.equal(state.e, 0x67);
assert.equal(state.b, 0xab);
assert.equal(state.c, 0xcd);
});

it('inx', () => {
let [state, mem] = runProg(`
lxi hl, 12ffh
Expand Down Expand Up @@ -547,13 +565,10 @@ loop:
`);

assert.ok(state.halted);
console.log(mem);

assert.equal(mem[labelToAddr.get('TargetArray')], 0x11);
assert.equal(mem[labelToAddr.get('TargetArray') + 1], 0x22);
assert.equal(mem[labelToAddr.get('TargetArray') + 2], 0x33);
assert.equal(mem[labelToAddr.get('TargetArray') + 3], 0x44);
assert.equal(mem[labelToAddr.get('TargetArray') + 4], 0x55);
});

});

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