Parse architecture from PyTorch instead of hard coding

[whitneywhtsang]

With pytorch/pytorch#138186, architecture is added to XPU device property.
Instead of hard coding pvc when invoking ocloc, this PR changed to dynamically passing the device architecture parsed.

[alexbaden]

LGTM, thanks!

[pbchekin]

Looks like this change makes CI slower (~2h vs ~1.5h).

[whitneywhtsang]

Looks like this change makes CI slower (~2h vs ~1.5h).

With 5e6d2c9, we verified that the supported extensions are unchanged, so the increase in CI time should be due to ocloc invocation, 89aa35d attempts to reduce the number of invocation by half.

[chengjunlu]

Looks like this change makes CI slower (~2h vs ~1.5h).

With 5e6d2c9, we verified that the supported extensions are unchanged, so the increase in CI time should be due to ocloc invocation, 89aa35d attempts to reduce the number of invocation by half.

Maybe we can cache the hardware capability to reduce the number call of ocloc further.

[whitneywhtsang]

Looks like this change makes CI slower (~2h vs ~1.5h).

With 5e6d2c9, we verified that the supported extensions are unchanged, so the increase in CI time should be due to ocloc invocation, 89aa35d attempts to reduce the number of invocation by half.

Maybe we can cache the hardware capability to reduce the number call of ocloc further.

New CI time is 1h 36m 48s, let's see how much more caching can reduce.

[whitneywhtsang]

Looks like this change makes CI slower (~2h vs ~1.5h).

With 5e6d2c9, we verified that the supported extensions are unchanged, so the increase in CI time should be due to ocloc invocation, 89aa35d attempts to reduce the number of invocation by half.

Maybe we can cache the hardware capability to reduce the number call of ocloc further.

New CI time is 1h 36m 48s, let's see if cache can reduce more in a different PR.

With caching, further reduced to 1h 25m 26s.