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105 Open 159 Closed
105 Open 159 Closed
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Issues list

Make assignments between packed LogicArrays and Logics in generated SystemVerilog avoid a swizzle enhancement New feature or request help wanted Extra attention is needed
#559 opened Jan 29, 2025 by mkorbel1
Add WASM compiliation support enhancement New feature or request help wanted Extra attention is needed
#554 opened Jan 21, 2025 by mkorbel1
Resolve driver vs. receiver based on usage for certain types of operations enhancement New feature or request
#553 opened Jan 21, 2025 by mkorbel1
Omit redundant parentheses in generated SystemVerilog enhancement New feature or request help wanted Extra attention is needed
#552 opened Jan 21, 2025 by mkorbel1
Mark bit ranges in swizzles in generated SystemVerilog enhancement New feature or request good first issue Good for newcomers
#551 opened Jan 21, 2025 by mkorbel1
Attaching a packed array port to an unpacked array port of a submodule generates bad SV bug Something isn't working help wanted Extra attention is needed
#549 opened Jan 15, 2025 by mkorbel1
Add optional source annotation in generated outputs enhancement New feature or request
#547 opened Jan 15, 2025 by mkorbel1
Mark dangling ports in module instantiations enhancement New feature or request help wanted Extra attention is needed
#546 opened Jan 15, 2025 by mkorbel1
Automatic sorting and grouping for generated outputs enhancement New feature or request help wanted Extra attention is needed
#545 opened Jan 15, 2025 by mkorbel1
1
Error when sub-modules are already built is confusing enhancement New feature or request
#544 opened Jan 15, 2025 by mkorbel1
Allow swizzles to be receivers of assignments in generated SystemVerilog for nets enhancement New feature or request
#530 opened Nov 22, 2024 by mkorbel1
Consts that inferWidth to 0-width generate SystemVerilog with 0-width bug Something isn't working help wanted Extra attention is needed
#527 opened Oct 14, 2024 by mkorbel1
Add documentation on Interfaces driving/receiving each other documentation Improvements or additions to documentation enhancement New feature or request help wanted Extra attention is needed
#524 opened Oct 4, 2024 by mkorbel1
Allow swizzling on Iterable instead of just List enhancement New feature or request good first issue Good for newcomers
#523 opened Oct 4, 2024 by mkorbel1
1
When replicating by 1, just return the 1 signal enhancement New feature or request good first issue Good for newcomers
#522 opened Oct 4, 2024 by mkorbel1
Add documentation for selectIndex and selectFrom in the user guide documentation Improvements or additions to documentation enhancement New feature or request good first issue Good for newcomers
#520 opened Oct 4, 2024 by mkorbel1
PairInterface cloning should include subInterfaces as well enhancement New feature or request help wanted Extra attention is needed
#519 opened Oct 4, 2024 by mkorbel1
Expose & infer name on automations like flop, cases, mux, etc. enhancement New feature or request good first issue Good for newcomers
#517 opened Oct 3, 2024 by mkorbel1
A way to dispose of unnecessary Simulator subscriptions enhancement New feature or request
#516 opened Oct 2, 2024 by mkorbel1
1
Interface._setPort assertion should be an exception bug Something isn't working good first issue Good for newcomers
#514 opened Sep 26, 2024 by mkorbel1
Add SystemVerilog generation control for top of module definition enhancement New feature or request
#513 opened Sep 26, 2024 by mkorbel1
Add automation to help with Lists of signals as ports of a module enhancement New feature or request good first issue Good for newcomers
#512 opened Sep 18, 2024 by mkorbel1
Dart code generation for common automation enhancement New feature or request
#511 opened Sep 18, 2024 by mkorbel1
1
Partial assignment of Logic indices enhancement New feature or request help wanted Extra attention is needed
#510 opened Sep 17, 2024 by mkorbel1
"Default" values for FiniteStateMachines enhancement New feature or request help wanted Extra attention is needed
#509 opened Sep 17, 2024 by mkorbel1
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