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verilog parser - parsing when port name has "input_" characters #9

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KyleJeong opened this issue May 26, 2018 · 0 comments
Open

verilog parser - parsing when port name has "input_" characters #9

KyleJeong opened this issue May 26, 2018 · 0 comments

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@KyleJeong
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This was the case I met.
input wire [29:0] input_data;

In that case, parser though that the port name is "_data".
liambeguin pushed a commit to liambeguin/hdlparse that referenced this issue Jul 6, 2023
@vvvverre
Update README (kevinpt#9)
a4fad04 
- Update URLs to point to hdl/pyHDLParser, not vvvverre/hdlparse.
- Remove the pip installation command, as the PyPI version is out of date.

Signed-off-by: Wouter van Verre <[email protected]>
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@KyleJeong