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14 Open 5 Closed
14 Open 5 Closed
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Issues list

Need Python 3 version of this library. No longer builds due to lack of use_2to3
#24 opened Jan 16, 2023 by Anutrix
2
Error in parsing the last Output
#23 opened Jun 25, 2022 by Eyantra698Sumanto
Does not look to be actively maintained
#21 opened Sep 12, 2021 by michael-etzkorn
14
Documentation bug extract_objects_from_source
#20 opened Sep 12, 2021 by michael-etzkorn
Parsing "output logic" port is wrong
#16 opened Apr 17, 2020 by masics
matching end of entity and end of architecture
#13 opened Mar 17, 2019 by m-tosch
1
1
Verilog and VHDL parser issues
#12 opened Oct 2, 2018 by nvzach
verilog parser - parse as a port of a function's port.
#11 opened May 26, 2018 by KyleJeong
verilog parser - Wrong parsing of comment
#10 opened May 26, 2018 by KyleJeong
verilog parser - parsing when port name has "input_" characters
#9 opened May 26, 2018 by KyleJeong
verilog parser struggled with 'output' as part of port name
#8 opened May 14, 2018 by Blechzwerg
Get hdlparse registered at awesome-vhdl
#7 opened May 5, 2018 by Paebbels
hdl parse not working for parsing an entity
#6 opened Apr 16, 2018 by obruendl
1
Support for Verilog 2001 attributes?
#5 opened Feb 21, 2018 by mithro
1
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