cont'd.

src/main/scala/ee/hrzn/chryse/platform/ElaboratablePlatform.scala

@@ -4,7 +4,5 @@ import chisel3._
 import ee.hrzn.chryse.ChryseModule
 
 trait ElaboratablePlatform extends Platform {
-  // TODO: make it easier to call plat(module).
-  // Maybe just make it top: Platform => Top and call them as plat(new Top(_)).
-  def apply[Top <: Module](top: => Top): ChryseModule
+  def apply[Top <: Module](top: Platform => Top): ChryseModule
 }

src/main/scala/ee/hrzn/chryse/platform/cxxrtl/CXXRTLPlatform.scala

@@ -3,12 +3,13 @@ package ee.hrzn.chryse.platform.cxxrtl
 import chisel3._
 import ee.hrzn.chryse.platform.ElaboratablePlatform
 import ee.hrzn.chryse.platform.GenericTop
+import ee.hrzn.chryse.platform.Platform
 
 final case class CXXRTLPlatform(options: CXXRTLOptions)
     extends ElaboratablePlatform {
   val id      = "cxxrtl"
   val clockHz = options.clockHz
 
-  override def apply[Top <: Module](top: => Top) =
-    GenericTop(this, top)
+  override def apply[Top <: Module](top: Platform => Top) =
+    GenericTop(this, top(this))
 }

src/main/scala/ee/hrzn/chryse/platform/ecp5/OrangeCrabPlatform.scala

@@ -3,10 +3,11 @@ package ee.hrzn.chryse.platform.ecp5
 import chisel3._
 import ee.hrzn.chryse.platform.BoardPlatform
 import ee.hrzn.chryse.platform.BoardResources
+import ee.hrzn.chryse.platform.Platform
 import ee.hrzn.chryse.platform.resource
 
-case object ECP5Platform extends BoardPlatform[ECP5Resources] {
-  val id      = "ecp5"
+case object OrangeCrabPlatform extends BoardPlatform[ECP5Resources] {
+  val id      = "orangecrab"
   val clockHz = 48_000_000
 
   // TODO: --25k? define somewhere.
@@ -17,8 +18,8 @@ case object ECP5Platform extends BoardPlatform[ECP5Resources] {
 
   val resources = new ECP5Resources
 
-  override def apply[Top <: Module](genTop: => Top) =
-    ECP5Top(this, genTop)
+  override def apply[Top <: Module](genTop: Platform => Top) =
+    ECP5Top(this, genTop(this))
 }
 
 class ECP5Resources extends BoardResources {

src/main/scala/ee/hrzn/chryse/platform/ice40/ICE40Top.scala

@@ -18,11 +18,14 @@ class ICE40Top[Top <: Module](
     platform: BoardPlatform[_ <: BoardResources],
     genTop: => Top,
 ) extends ChryseModule {
-  override def desiredName = "top"
+  import platform.resources.clock.Implicits._
+
+  override def desiredName = "ice40top"
+
+  val clki = Wire(Clock())
 
   private val clk_gb = Module(new SB_GB)
-  import platform.resources.clock.Implicits._
-  clk_gb.USER_SIGNAL_TO_GLOBAL_BUFFER := platform.resources.clock
+  clk_gb.USER_SIGNAL_TO_GLOBAL_BUFFER := clki
   private val clk = clk_gb.GLOBAL_BUFFER_OUTPUT
 
   private val timerLimit = (15e-6 * platform.clockHz).toInt
@@ -38,6 +41,7 @@ class ICE40Top[Top <: Module](
   }
 
   val finalReset = noPrefix {
+    // TODO: this no longer works. :)
     if (platform.asInstanceOf[IceBreakerPlatform].ubtnReset) {
       val io_ubtn = IO(Input(Bool()))
       reset | ~io_ubtn
@@ -57,6 +61,16 @@ class ICE40Top[Top <: Module](
     val name = f.getName()
     f.setAccessible(true)
     f.get(platform.resources) match {
+      case clock: resource.ClockSource =>
+        if (clock.inst.isDefined) {
+          throw new Exception("clock must be manually handled for now")
+        }
+        // NOTE: we can't just say clki := platform.resources.clock in our top
+        // here, since that'll define an input IO in *this* module which we
+        // can't then sink like we would in the resource.Base[_] case.
+        sb.append(s"set_io $name ${clock.pinId.get}\n")
+        clki := IO(Input(Clock())).suggestName(name)
+
       case res: resource.Base[_] =>
         if (res.inst.isDefined) {
           sb.append(s"set_io $name ${res.pinId.get}\n")

src/main/scala/ee/hrzn/chryse/platform/ice40/IceBreakerPlatform.scala

@@ -3,6 +3,7 @@ package ee.hrzn.chryse.platform.ice40
 import chisel3._
 import ee.hrzn.chryse.platform.BoardPlatform
 import ee.hrzn.chryse.platform.BoardResources
+import ee.hrzn.chryse.platform.Platform
 import ee.hrzn.chryse.platform.resource
 import ee.hrzn.chryse.platform.resource.Pin._
 
@@ -18,8 +19,8 @@ final case class IceBreakerPlatform(ubtnReset: Boolean = false)
 
   val resources = new IceBreakerResources
 
-  override def apply[Top <: Module](genTop: => Top) =
-    ICE40Top(this, genTop)
+  override def apply[Top <: Module](genTop: Platform => Top) =
+    ICE40Top(this, genTop(this))
 }
 
 class IceBreakerResources extends BoardResources {

src/main/scala/ee/hrzn/chryse/platform/resource/Base.scala

@@ -13,7 +13,7 @@ trait Base[HW <: Data] {
     inst match {
       case Some(r) => r
       case None =>
-        val r = IO(make()).suggestName(s"${name.get}_internal")
+        val r = IO(make()).suggestName(s"${name.get}_int")
         inst = Some(r)
         inst.get
     }

src/main/scala/ee/hrzn/chryse/platform/resource/BaseInBool.scala

@@ -1,36 +1,5 @@
 package ee.hrzn.chryse.platform.resource
 
 import chisel3._
-import chisel3.experimental.dataview._
 
-import scala.language.implicitConversions
-
-class BaseInBool extends Base[Bool] {
-  private var invert = false // TODO: invert should do something
-
-  private[chryse] def make(): Bool = Input(Bool())
-
-  def inverted: this.type = {
-    invert = true
-    this
-  }
-}
-
-object BaseInBool {
-  object Implicits {
-    implicit val BaseInBoolProduct: DataProduct[BaseInBool] =
-      new DataProduct[BaseInBool] {
-        def dataIterator(
-            res: BaseInBool,
-            path: String,
-        ): Iterator[(Data, String)] =
-          List(res.inst.get -> path).iterator
-      }
-
-    implicit def view: DataView[BaseInBool, Bool] =
-      DataView(res => Bool(), _.instOrMake() -> _)
-
-    implicit def BaseInBool2Bool(res: BaseInBool): Bool =
-      res.viewAs[Bool]
-  }
-}
+object BaseInBool extends BaseIn[Bool](Bool()) {}

src/main/scala/ee/hrzn/chryse/platform/resource/BaseOut.scala

@@ -0,0 +1,27 @@
+package ee.hrzn.chryse.platform.resource
+
+import chisel3._
+import chisel3.experimental.dataview._
+
+import scala.language.implicitConversions
+
+class BaseOut[HW <: Data](gen: => HW) extends Base[HW] {
+  private[chryse] def make(): HW = Output(gen)
+
+  object Implicits {
+    implicit val BaseOutProduct: DataProduct[BaseOut[HW]] =
+      new DataProduct[BaseOut[HW]] {
+        def dataIterator(
+            res: BaseOut[HW],
+            path: String,
+        ): Iterator[(Data, String)] =
+          List(res.inst.get -> path).iterator
+      }
+
+    implicit def view: DataView[BaseOut[HW], HW] =
+      DataView(res => gen, _.instOrMake() -> _)
+
+    implicit def BaseOut2HW(res: BaseOut[HW]): HW =
+      res.viewAs[HW]
+  }
+}

src/main/scala/ee/hrzn/chryse/platform/resource/BaseOutBool.scala

@@ -1,36 +1,5 @@
 package ee.hrzn.chryse.platform.resource
 
 import chisel3._
-import chisel3.experimental.dataview._
 
-import scala.language.implicitConversions
-
-class BaseOutBool extends Base[Bool] {
-  private var invert = false // TODO: invert should do something
-
-  private[chryse] def make(): Bool = Output(Bool())
-
-  def inverted: this.type = {
-    invert = true
-    this
-  }
-}
-
-object BaseOutBool {
-  object Implicits {
-    implicit val BaseOutBoolProduct: DataProduct[BaseOutBool] =
-      new DataProduct[BaseOutBool] {
-        def dataIterator(
-            res: BaseOutBool,
-            path: String,
-        ): Iterator[(Data, String)] =
-          List(res.inst.get -> path).iterator
-      }
-
-    implicit def view: DataView[BaseOutBool, Bool] =
-      DataView(res => Bool(), _.instOrMake() -> _)
-
-    implicit def BaseOutBool2Bool(res: BaseOutBool): Bool =
-      res.viewAs[Bool]
-  }
-}
+object BaseOutBool extends BaseOut[Bool](Bool()) {}

src/main/scala/ee/hrzn/chryse/platform/resource/Button.scala

@@ -1,6 +1,15 @@
 package ee.hrzn.chryse.platform.resource
 
-class Button extends BaseInBool {}
+import chisel3._
+
+class Button extends BaseIn[Bool](Bool()) {
+  private var invert = false // TODO: invert should do something, and possibly belongs in a higher class
+
+  def inverted: this.type = {
+    invert = true
+    this
+  }
+}
 
 object Button {
   def apply() = new Button

src/main/scala/ee/hrzn/chryse/platform/resource/LED.scala

@@ -1,6 +1,15 @@
 package ee.hrzn.chryse.platform.resource
 
-class LED extends BaseOutBool {}
+import chisel3._
+
+class LED extends BaseOut[Bool](Bool()) {
+  private var invert = false // TODO: invert should do something, and possibly belongs in a higher class
+
+  def inverted: this.type = {
+    invert = true
+    this
+  }
+}
 
 object LED {
   def apply() = new LED

src/main/scala/ee/hrzn/chryse/platform/resource/Pin.scala

@@ -3,8 +3,12 @@ package ee.hrzn.chryse.platform.resource
 import scala.language.implicitConversions
 
 sealed trait Pin
-case class PinString(p: String) extends Pin
-case class PinInt(p: Int)       extends Pin
+case class PinString(p: String) extends Pin {
+  override def toString(): String = p
+}
+case class PinInt(p: Int) extends Pin {
+  override def toString(): String = s"$p"
+}
 
 object Pin {
   implicit def string2Pin(p: String): Pin = PinString(p)

src/main/scala/ee/hrzn/chryse/platform/resource/UARTRX.scala

@@ -1,6 +1,8 @@
 package ee.hrzn.chryse.platform.resource
 
-class UARTRX extends BaseInBool {}
+import chisel3._
+
+class UARTRX extends BaseIn[Bool](Bool()) {}
 
 object UARTRX {
   def apply() = new UARTRX

src/main/scala/ee/hrzn/chryse/platform/resource/UARTTX.scala

@@ -1,6 +1,8 @@
 package ee.hrzn.chryse.platform.resource
 
-class UARTTX extends BaseOutBool {}
+import chisel3._
+
+class UARTTX extends BaseOut[Bool](Bool()) {}
 
 object UARTTX {
   def apply() = new UARTTX

src/main/scala/ee/hrzn/chryse/tasks/BuildTask.scala

@@ -27,7 +27,7 @@ object BuildTask extends BaseTask {
     val verilog =
       ChiselStage.emitSystemVerilog(
         {
-          val elaborated = platform(genTop(platform))
+          val elaborated = platform(genTop)
           lastPCF = elaborated.lastPCF
           elaborated
         },

src/main/scala/ee/hrzn/chryse/tasks/CxxsimTask.scala

@@ -35,7 +35,7 @@ object CxxsimTask extends BaseTask {
     val verilogPath = s"$buildDir/$name-${platform.id}.sv"
     val verilog =
       ChiselStage.emitSystemVerilog(
-        platform(genTop(platform)),
+        platform(genTop),
         firtoolOpts = firtoolOpts,
       )
     writePath(verilogPath, verilog)

src/test/scala/ee/hrzn/chryse/platform/BoardResourcesSpec.scala

@@ -17,10 +17,11 @@ class BoardResourcesSpec extends AnyFlatSpec with Matchers {
   it should "detect resource uses and generate PCFs accordingly" in {
     val plat = IceBreakerPlatform()
     val top = BuilderContext {
-      plat(new DetectionTop(plat))
+      plat(new DetectionTop(_))
     }
     top.lastPCF.get.linesIterator.toList.sorted.mkString("\n") should be(
-      """set_io ledg 37
+      """set_io clock 35
+        |set_io ledg 37
         |set_io uart_rx 6
         |set_io uart_tx 9
         |set_io ubtn 10""".stripMargin,
@@ -31,15 +32,18 @@ class BoardResourcesSpec extends AnyFlatSpec with Matchers {
     val plat             = IceBreakerPlatform()
     var top: ICE40Top[_] = null
     val rtl = ChiselStage.emitSystemVerilog {
-      top = plat(new InversionTop(plat))
+      top = plat(new InversionTop(_))
       top
     }
     top.lastPCF.get.linesIterator.toList.sorted.mkString("\n") should be(
-      """set_io ledg 37
+      """set_io clock 35
+        |set_io ledg 37
         |set_io uart_tx 9
         |set_io ubtn 10""".stripMargin,
     )
-    rtl should be("")
+    rtl should include("ledg_int = view__ubtn_int")
+    (rtl should not).include("uart_tx_int = view__ubtn_int")
+    rtl should include("uart_tx_int = ~view__ubtn_int")
   }
 }