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name: update dependency graph | ||
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on: | ||
push: | ||
branches: | ||
- main | ||
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permissions: | ||
contents: write | ||
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jobs: | ||
dependency-graph: | ||
runs-on: ubuntu-latest | ||
steps: | ||
- name: Checkout chryse | ||
uses: actions/checkout@v4 | ||
with: | ||
repository: kivikakk/chryse | ||
- name: Set up JDK 22 | ||
uses: actions/setup-java@v4 | ||
with: | ||
java-version: '22' | ||
distribution: 'temurin' | ||
cache: 'sbt' | ||
- name: Build and install chryse locally | ||
run: sbt publishLocal | ||
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- name: Checkout this | ||
uses: actions/checkout@v4 | ||
- uses: scalacenter/sbt-dependency-submission@v2 |
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name: iCE40 synthesis | ||
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on: | ||
push: | ||
branches: [ "main" ] | ||
pull_request: | ||
branches: [ "main" ] | ||
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permissions: | ||
contents: read | ||
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jobs: | ||
build: | ||
runs-on: ubuntu-latest | ||
steps: | ||
- name: Checkout chryse | ||
uses: actions/checkout@v4 | ||
with: | ||
repository: kivikakk/chryse | ||
- name: Set up JDK 22 | ||
uses: actions/setup-java@v4 | ||
with: | ||
java-version: '22' | ||
distribution: 'temurin' | ||
cache: 'sbt' | ||
- name: Build and install chryse locally | ||
run: sbt publishLocal | ||
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- name: Install OSS CAD Suite | ||
uses: YosysHQ/setup-oss-cad-suite@v3 | ||
with: | ||
github-token: ${{ secrets.GITHUB_TOKEN }} | ||
- run: yosys --version | ||
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- name: Checkout this | ||
uses: actions/checkout@v4 | ||
- name: Elaborate | ||
run: sbt run | ||
- name: Synthesise | ||
run: make ice40 |
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name: Unit tests | ||
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on: | ||
push: | ||
branches: [ "main" ] | ||
pull_request: | ||
branches: [ "main" ] | ||
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permissions: | ||
contents: read | ||
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||
jobs: | ||
build: | ||
runs-on: ubuntu-latest | ||
steps: | ||
- name: Checkout chryse | ||
uses: actions/checkout@v4 | ||
with: | ||
repository: kivikakk/chryse | ||
- name: Set up JDK 22 | ||
uses: actions/setup-java@v4 | ||
with: | ||
java-version: '22' | ||
distribution: 'temurin' | ||
cache: 'sbt' | ||
- name: Build and install chryse locally | ||
run: sbt publishLocal | ||
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- name: Checkout this | ||
uses: actions/checkout@v4 | ||
- name: Run tests | ||
run: sbt test |
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build/ | ||
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*.asc | ||
*.bin | ||
*.vcd | ||
*.json | ||
*.rpt | ||
*.tim | ||
*.sv | ||
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target/ | ||
test_run_dir/ | ||
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.metals/ | ||
.bloop/ | ||
metals.sbt | ||
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.DS_Store |
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version = "3.7.15" | ||
runner.dialect = scala213 | ||
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maxColumn = 80 | ||
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newlines.avoidForSimpleOverflow = [slc, tooLong] | ||
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assumeStandardLibraryStripMargin = true | ||
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align.preset = most | ||
align.multiline = false | ||
align.tokens."+" = [ | ||
{ code = ":=", owner = "Term.ApplyInfix" }, | ||
{ code = "+=", owner = "Term.ApplyInfix" }, | ||
{ code = "++=", owner = "Term.ApplyInfix" }, | ||
{ code = "--=", owner = "Term.ApplyInfix" }, | ||
{ code = "-=", owner = "Term.ApplyInfix" }, | ||
] | ||
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binPack.literalArgumentLists = true | ||
binPack.literalsIncludeSimpleExpr = true | ||
binPack.literalsExclude = [ "Term.Name" ] | ||
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# do I care about this? | ||
docstrings.style = "SpaceAsterisk" | ||
docstrings.wrap = yes | ||
docstrings.oneline = fold | ||
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rewrite.rules = [ | ||
AvoidInfix, # do I want this? | ||
RedundantBraces, | ||
RedundantParens, | ||
SortModifiers, | ||
PreferCurlyFors, | ||
Imports, | ||
] | ||
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rewrite.redundantBraces.maxBreaks = 1 | ||
rewrite.redundantBraces.stringInterpolation = true | ||
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rewrite.trailingCommas.style = always | ||
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# unsure. | ||
# includeCurlyBraceInSelectChains = false | ||
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project.includePaths = ["glob:**.scala", "glob:**.sbt", "glob:**.sc", "glob:**.md"] | ||
project.excludePaths = ["glob:**metals.sbt"] |
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BASENAME = Top | ||
BUILD_DIR = build | ||
ARTIFACT_PREFIX = $(BUILD_DIR)/$(BASENAME) | ||
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SCALA_SRCS = $(shell find src/main/scala) | ||
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.PHONY: ice40-prog clean | ||
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all: | ||
@echo "Targets:" | ||
@echo " make ice40" | ||
@echo " make ice40-prog" | ||
@echo " make clean" | ||
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clean: | ||
-rm build/* | ||
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$(BASENAME)-%.sv: $(SCALA_SRCS) | ||
sbt run | ||
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ice40: $(ARTIFACT_PREFIX).bin | ||
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ice40-prog: $(ARTIFACT_PREFIX).bin | ||
iceprog $< | ||
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$(ARTIFACT_PREFIX).bin: $(ARTIFACT_PREFIX).asc | ||
icepack $< $@ | ||
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$(ARTIFACT_PREFIX).asc: $(ARTIFACT_PREFIX).json $(BASENAME)-ice40.pcf | ||
nextpnr-ice40 -q --log $(ARTIFACT_PREFIX).tim \ | ||
--up5k --package sg48 \ | ||
--json $(ARTIFACT_PREFIX).json \ | ||
--pcf $(BASENAME)-ice40.pcf \ | ||
--asc $@ | ||
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$(ARTIFACT_PREFIX).json: $(BASENAME)-ice40.sv | ||
@mkdir -p $(BUILD_DIR) | ||
yosys -q -g -l $(ARTIFACT_PREFIX).rpt \ | ||
-p 'read_verilog -sv $<' \ | ||
-p 'synth_ice40 -top top' \ | ||
-p 'write_json $@' |
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set_io clki 35 | ||
set_frequency clki 12.0 | ||
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set_io io_ubtn 10 | ||
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set_io io_ledr 11 | ||
set_io io_ledg 37 |
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import scala.sys.process._ | ||
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ThisBuild / scalaVersion := "2.13.12" | ||
ThisBuild / version := "0.1.0" | ||
ThisBuild / organization := "com.example" | ||
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val chiselVersion = "6.3.0" | ||
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lazy val root = (project in file(".")) | ||
.settings( | ||
name := "newproject", | ||
libraryDependencies ++= Seq( | ||
"org.chipsalliance" %% "chisel" % chiselVersion, | ||
"org.scalatest" %% "scalatest" % "3.2.18" % "test", | ||
"edu.berkeley.cs" %% "chiseltest" % "6.0.0", | ||
"ee.hrzn" %% "chryse" % "0.1.0-SNAPSHOT", | ||
), | ||
scalacOptions ++= Seq( | ||
"-language:reflectiveCalls", "-deprecation", "-feature", "-Xcheckinit", | ||
"-Ymacro-annotations", | ||
), | ||
addCompilerPlugin( | ||
"org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full, | ||
), | ||
) | ||
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// TODO: we want to move these into chryse itself, to be imported into projects that use it. | ||
// Same for cxxsim stuff. | ||
lazy val ice40 = inputKey[Unit]("Elaborate and synthesise for ice40") | ||
ice40 := { | ||
(Compile / run).evaluated | ||
if (("make ice40" !) != 0) { | ||
throw new IllegalStateException("ice40 failed to synthesise") | ||
} | ||
} | ||
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lazy val ice40prog = | ||
inputKey[Unit]("Elaborate, synthesise for ice40, and program the board") | ||
ice40prog := { | ||
(Compile / run).evaluated | ||
if (("make ice40-prog" !) != 0) { | ||
throw new IllegalStateException("ice40 failed to synthesise") | ||
} | ||
} |
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sbt.version = 1.9.7 |
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logLevel := Level.Warn |
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package com.example.newproject | ||
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import _root_.circt.stage.ChiselStage | ||
import chisel3._ | ||
import chisel3.util._ | ||
import ee.hrzn.chryse.HasIO | ||
import ee.hrzn.chryse.platform.ElaboratablePlatform | ||
import ee.hrzn.chryse.platform.Platform | ||
import ee.hrzn.chryse.platform.ice40.ICE40Platform | ||
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import java.io.PrintWriter | ||
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class TopIO extends Bundle { | ||
val ledr = Output(Bool()) | ||
val ledg = Output(Bool()) | ||
} | ||
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class Top(implicit platform: Platform) extends Module with HasIO[TopIO] { | ||
def createIo() = new TopIO | ||
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private val ledReg = RegInit(true.B) | ||
io.ledr := ledReg | ||
val timerReg = RegInit( | ||
((platform.clockHz / 4) - 1) | ||
.U(unsignedBitLength((platform.clockHz / 2) - 1).W), | ||
) | ||
when(timerReg === 0.U) { | ||
ledReg := ~ledReg | ||
timerReg := ((platform.clockHz / 2) - 1).U | ||
}.otherwise { | ||
timerReg := timerReg - 1.U | ||
} | ||
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io.ledg := false.B | ||
} | ||
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object Top extends App { | ||
def apply()(implicit platform: ElaboratablePlatform) = | ||
platform(new Top) | ||
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implicit private val platform: ElaboratablePlatform = ICE40Platform | ||
private val firtoolOpts = Array( | ||
"--lowering-options=disallowLocalVariables", | ||
"-disable-all-randomization", | ||
"-strip-debug-info", | ||
) | ||
val verilog = | ||
ChiselStage.emitSystemVerilog(Top(), firtoolOpts = firtoolOpts) | ||
new PrintWriter(s"Top-${platform.id}.sv", "utf-8") { | ||
try | ||
write(verilog) | ||
finally close() | ||
} | ||
} |
28 changes: 28 additions & 0 deletions
28
template/src/test/scala/com/example/newproject/TopSpec.scala
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package com.example.newproject | ||
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import chisel3._ | ||
import chiseltest._ | ||
import chiseltest.simulator.WriteVcdAnnotation | ||
import ee.hrzn.chryse.platform.Platform | ||
import org.scalatest.flatspec.AnyFlatSpec | ||
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class TopSpec extends AnyFlatSpec with ChiselScalatestTester { | ||
behavior.of("Top") | ||
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implicit private val platform: Platform = new Platform { | ||
val id = "topspec" | ||
val clockHz = 8 | ||
} | ||
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it should "blink the light" in { | ||
test(new Top()).withAnnotations(Seq(WriteVcdAnnotation)) { c => | ||
// ledg is always false (on). | ||
// ledr starts true (off) for 1/4 duty, then toggles evenly at 1/2 duty. | ||
for { ledr <- Seq(1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1) } { | ||
c.io.ledg.expect(false.B) | ||
c.io.ledr.expect((ledr == 1).B) | ||
c.clock.step() | ||
} | ||
} | ||
} | ||
} |