just using Seq for now.

src/main/scala/ee/hrzn/chryse/platform/BoardResources.scala

@@ -19,5 +19,5 @@ abstract class BoardResources {
 
   val clock: resource.ClockSource
 
-  def all: List[Base[_ <: Data]] = Resource.allFromBoardResources(this)
+  def all: Seq[Base[_ <: Data]] = Resource.allFromBoardResources(this)
 }

src/main/scala/ee/hrzn/chryse/platform/cxxrtl/CXXRTLOptions.scala

@@ -4,7 +4,6 @@ import chisel3.BlackBox
 
 import scala.sys.process._
 
-// XXX: Seq or List better?
 final case class CXXRTLOptions(
     clockHz: Int,
     blackboxes: Seq[Class[_ <: BlackBox]] = Seq(),

src/main/scala/ee/hrzn/chryse/platform/resource/Base.scala

@@ -31,7 +31,7 @@ abstract class Base[HW <: Data](gen: => HW) extends Resource {
     this
   }
 
-  def bases(): List[Base[_ <: Data]] = List(this)
+  def bases(): Seq[Base[_ <: Data]] = Seq(this)
 }
 
 case class InstSides[HW](user: HW, top: HW)

src/main/scala/ee/hrzn/chryse/platform/resource/InOut.scala

@@ -17,7 +17,7 @@ class InOut extends Resource {
     this
   }
 
-  def bases(): List[Base[_ <: Data]] = List(i, o)
+  def bases(): Seq[Base[_ <: Data]] = Seq(i, o)
 }
 
 object InOut {

src/main/scala/ee/hrzn/chryse/platform/resource/Resource.scala

@@ -7,13 +7,13 @@ import scala.collection.mutable.ArrayBuffer
 
 trait Resource {
   def setName(name: String): Unit
-  def bases(): List[Base[_ <: Data]]
+  def bases(): Seq[Base[_ <: Data]]
 }
 
 object Resource {
   def allFromBoardResources[T <: BoardResources](
       br: T,
-  ): List[Base[_ <: Data]] = {
+  ): Seq[Base[_ <: Data]] = {
     var out = ArrayBuffer[Base[_ <: Data]]()
     for { f <- br.getClass().getDeclaredFields().iterator } {
       f.setAccessible(true)
@@ -23,6 +23,6 @@ object Resource {
         case _ =>
       }
     }
-    out.toList
+    out.toSeq
   }
 }

src/main/scala/ee/hrzn/chryse/platform/resource/UART.scala

@@ -17,7 +17,7 @@ class UART extends Resource {
     this
   }
 
-  def bases(): List[Base[_ <: Data]] = List(rx, tx)
+  def bases(): Seq[Base[_ <: Data]] = Seq(rx, tx)
 }
 
 object UART {

src/main/scala/ee/hrzn/chryse/platform/resource/implicits.scala

@@ -15,7 +15,7 @@ object implicits {
           res: Base[HW],
           path: String,
       ): Iterator[(Data, String)] =
-        List(res.ioInst.get.user -> path).iterator
+        Seq(res.ioInst.get.user -> path).iterator
     }
 
   implicit def viewBool: DataView[Base[Bool], Bool] =

src/main/scala/ee/hrzn/chryse/tasks/CxxsimTask.scala

@@ -24,7 +24,7 @@ object CxxsimTask extends BaseTask {
       optimize: Boolean,
       compileOnly: Boolean,
       vcdOutPath: Option[String],
-      args: List[String],
+      args: Seq[String],
   )
 
   def apply[Top <: Module](

src/main/scala/ee/hrzn/chryse/verilog/InterfaceExtractor.scala

@@ -17,9 +17,9 @@ object InterfaceExtractor {
       raw"\s*(\w+)").r
 
   case class Module(
-      inputs: List[String] = List.empty,
-      outputs: List[String] = List.empty,
-      inouts: List[String] = List.empty,
+      inputs: Seq[String] = Seq.empty,
+      outputs: Seq[String] = Seq.empty,
+      inouts: Seq[String] = Seq.empty,
   )
 
   sealed private trait Mode
@@ -31,14 +31,14 @@ object InterfaceExtractor {
   def apply(sv: String): Map[String, Module] = {
     var map = mutable.Map[String, Module]()
     for {
-      List(moduleName, contents) <- reWhole.findAllMatchIn(sv).map(_.subgroups)
+      Seq(moduleName, contents) <- reWhole.findAllMatchIn(sv).map(_.subgroups)
     } {
       var mode: Mode = ModeNone
-      var inputs     = List[String]()
-      var outputs    = List[String]()
-      var inouts     = List[String]()
+      var inputs     = Seq[String]()
+      var outputs    = Seq[String]()
+      var inouts     = Seq[String]()
       for { el <- contents.split(",") if el.strip().length() != 0 } {
-        val List(kind, name) = reIndividual.findAllMatchIn(el).next().subgroups
+        val Seq(kind, name) = reIndividual.findAllMatchIn(el).next().subgroups
         kind match {
           case "input"  => mode = ModeInput
           case "output" => mode = ModeOutput

src/test/scala/ee/hrzn/chryse/platform/BoardResourcesSpec.scala

@@ -71,8 +71,8 @@ class BoardResourcesSpec extends AnyFlatSpec with Matchers {
 
     verilog.InterfaceExtractor(rtl) should contain(
       "chrysetop" -> verilog.InterfaceExtractor.Module(
-        inputs = List("clock", "ubtn"),
-        outputs = List("uart_tx", "ledg"),
+        inputs = Seq("clock", "ubtn"),
+        outputs = Seq("uart_tx", "ledg"),
       ),
     )
   }
@@ -105,8 +105,8 @@ class BoardResourcesSpec extends AnyFlatSpec with Matchers {
 
     verilog.InterfaceExtractor(rtl) should contain(
       "chrysetop" -> verilog.InterfaceExtractor.Module(
-        inputs = List("clock", "ubtn", "uart_rx", "pmod1a2", "pmod1b2"),
-        outputs = List("uart_tx", "ledr", "pmod1a1", "pmod1b1"),
+        inputs = Seq("clock", "ubtn", "uart_rx", "pmod1a2", "pmod1b2"),
+        outputs = Seq("uart_tx", "ledr", "pmod1a1", "pmod1b1"),
       ),
     )
   }

src/test/scala/ee/hrzn/chryse/verilog/InterfaceExtractorSpec.scala

@@ -20,7 +20,7 @@ class InterfaceExtractorSpec extends AnyFlatSpec with Matchers {
                          |""".stripMargin) should be(
       Map(
         "chrysetop" -> InterfaceExtractor.Module(
-          inputs = List("clock", "reset"),
+          inputs = Seq("clock", "reset"),
         ),
       ),
     )
@@ -65,13 +65,13 @@ class InterfaceExtractorSpec extends AnyFlatSpec with Matchers {
     ) should be(
       Map(
         "SevSeg" -> InterfaceExtractor.Module(
-          inputs = List("io_char"),
-          outputs = (for { i <- 0 until 7 } yield s"io_abcdefg_$i").toList,
+          inputs = Seq("io_char"),
+          outputs = (for { i <- 0 until 7 } yield s"io_abcdefg_$i").toSeq,
         ),
         "Top" -> InterfaceExtractor.Module(
-          inputs = List("clock", "reset", "def"),
-          outputs = List("xyz"),
-          inouts = List("abc"),
+          inputs = Seq("clock", "reset", "def"),
+          outputs = Seq("xyz"),
+          inouts = Seq("abc"),
         ),
       ),
     )