add cxx/ldFlags.

kivikakk · May 16, 2024 · 70721ac · 70721ac
1 parent 563a4ca
commit 70721ac
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Showing 3 changed files with 13 additions and 4 deletions.
diff --git a/.vscode/settings.json b/.vscode/settings.json
@@ -1,5 +1,6 @@
 {
     "files.watcherExclude": {
         "**/target": true
-    }
+    },
+    "editor.formatOnSave": true,
 }
diff --git a/src/main/scala/ee/hrzn/chryse/platform/cxxrtl/CXXRTLOptions.scala b/src/main/scala/ee/hrzn/chryse/platform/cxxrtl/CXXRTLOptions.scala
@@ -5,4 +5,6 @@ import chisel3.BlackBox
 final case class CXXRTLOptions(
     clockHz: Int,
     blackboxes: Seq[Class[_ <: BlackBox]] = Seq(),
+    cxxFlags: Seq[String] = Seq(),
+    ldFlags: Seq[String] = Seq(),
 )
diff --git a/src/main/scala/ee/hrzn/chryse/tasks/CxxsimTask.scala b/src/main/scala/ee/hrzn/chryse/tasks/CxxsimTask.scala
@@ -137,7 +137,7 @@ object CxxsimTask extends BaseTask {
       cc,
       "-o",
       obj,
-    ) ++ cxxOpts
+    ) ++ cxxOpts ++ cxxrtlOptions.cxxFlags
 
     // XXX: depend on what look like headers for now.
     val cus = for {
@@ -161,7 +161,9 @@ object CxxsimTask extends BaseTask {
       None,
       cus.map(_.outPath),
       binPath,
-      Seq("c++", "-o", binPath) ++ cxxOpts ++ cus.map(_.outPath),
+      Seq("c++", "-o", binPath) ++ cxxOpts ++ cus.map(
+        _.outPath,
+      ) ++ cxxrtlOptions.ldFlags,
     )
     runCu("linking", linkCu)
 
@@ -188,7 +190,11 @@ object CxxsimTask extends BaseTask {
       .filter(_.endsWith(ext))
 }
 
-private case class ClangdEntry(directory: String, file: String, arguments: Seq[String])
+private case class ClangdEntry(
+    directory: String,
+    file: String,
+    arguments: Seq[String],
+)
 private object ClangdEntry {
   implicit val rw: upickle.default.ReadWriter[ClangdEntry] =
     upickle.default.macroRW