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big-endian naming.
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kivikakk committed May 22, 2024
1 parent 94986ac commit acadb6a
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Showing 20 changed files with 119 additions and 61 deletions.
6 changes: 3 additions & 3 deletions src/main/scala/ee/hrzn/chryse/ChryseApp.scala
Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,9 @@ package ee.hrzn.chryse

import chisel3._
import circt.stage.ChiselStage
import ee.hrzn.chryse.platform.BoardPlatform
import ee.hrzn.chryse.platform.BoardResources
import ee.hrzn.chryse.platform.Platform
import ee.hrzn.chryse.platform.PlatformBoard
import ee.hrzn.chryse.platform.PlatformBoardResources
import ee.hrzn.chryse.platform.cxxrtl.CXXRTLOptions
import org.rogach.scallop._

Expand All @@ -13,7 +13,7 @@ import scala.collection.mutable
abstract class ChryseApp {
val name: String
val genTop: Platform => Module
val targetPlatforms: Seq[BoardPlatform[_ <: BoardResources]]
val targetPlatforms: Seq[PlatformBoard[_ <: PlatformBoardResources]]
val cxxrtlOptions: Option[CXXRTLOptions] = None

def main(args: Array[String]): Unit = {
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Expand Up @@ -2,13 +2,14 @@ package ee.hrzn.chryse.platform

import chisel3._

trait BoardPlatform[BR <: BoardResources] extends ElaboratablePlatform {
trait PlatformBoard[PBR <: PlatformBoardResources]
extends ElaboratablePlatform {
val nextpnrBinary: String
val nextpnrArgs: Seq[String]

val packBinary: String

val programBinary: String

val resources: BR
val resources: PBR
}
Original file line number Diff line number Diff line change
@@ -1,23 +1,24 @@
package ee.hrzn.chryse.platform

import chisel3._
import ee.hrzn.chryse.platform.resource.DataResource
import ee.hrzn.chryse.platform.resource.Base
import ee.hrzn.chryse.platform.resource.ResourceBase
import ee.hrzn.chryse.platform.resource.ResourceData

import scala.collection.mutable.ArrayBuffer

abstract class BoardResources {
abstract class PlatformBoardResources {
private[chryse] def setNames() =
for { f <- this.getClass().getDeclaredFields() } {
f.setAccessible(true)
f.get(this) match {
case res: Base =>
case res: ResourceBase =>
res.setName(f.getName())
case _ =>
}
}

val clock: resource.ClockSource

def all: Seq[DataResource[_ <: Data]] = Base.allFromBoardResources(this)
def all: Seq[ResourceData[_ <: Data]] =
ResourceBase.allFromBoardResources(this)
}
6 changes: 3 additions & 3 deletions src/main/scala/ee/hrzn/chryse/platform/ecp5/ECP5Top.scala
Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,9 @@ package ee.hrzn.chryse.platform.ecp5

import chisel3._
import ee.hrzn.chryse.ChryseModule
import ee.hrzn.chryse.platform.BoardPlatform
import ee.hrzn.chryse.platform.BoardResources
import ee.hrzn.chryse.platform.Platform
import ee.hrzn.chryse.platform.PlatformBoard
import ee.hrzn.chryse.platform.PlatformBoardResources

class ECP5Top[Top <: Module](platform: Platform, genTop: => Top)
extends ChryseModule {
Expand All @@ -28,7 +28,7 @@ class ECP5Top[Top <: Module](platform: Platform, genTop: => Top)

object ECP5Top {
def apply[Top <: Module](
platform: BoardPlatform[_ <: BoardResources],
platform: PlatformBoard[_ <: PlatformBoardResources],
genTop: => Top,
) =
new ECP5Top(platform, genTop)
Expand Down
Original file line number Diff line number Diff line change
@@ -1,12 +1,13 @@
package ee.hrzn.chryse.platform.ecp5

import chisel3._
import ee.hrzn.chryse.platform.BoardPlatform
import ee.hrzn.chryse.platform.BoardResources
import ee.hrzn.chryse.platform.Platform
import ee.hrzn.chryse.platform.PlatformBoard
import ee.hrzn.chryse.platform.PlatformBoardResources
import ee.hrzn.chryse.platform.resource

case object OrangeCrabPlatform extends BoardPlatform[ECP5Resources] {
case object OrangeCrabPlatform
extends PlatformBoard[OrangeCrabPlatformResources] {
val id = "orangecrab"
val clockHz = 48_000_000

Expand All @@ -16,12 +17,12 @@ case object OrangeCrabPlatform extends BoardPlatform[ECP5Resources] {
val packBinary = "ecppack"
val programBinary = "dfu-util"

val resources = new ECP5Resources
val resources = new OrangeCrabPlatformResources

override def apply[Top <: Module](genTop: Platform => Top) =
ECP5Top(this, genTop(this))
}

class ECP5Resources extends BoardResources {
class OrangeCrabPlatformResources extends PlatformBoardResources {
val clock = resource.ClockSource(48_000_000).onPin("A9")
}
8 changes: 5 additions & 3 deletions src/main/scala/ee/hrzn/chryse/platform/ice40/ICE40Top.scala
Original file line number Diff line number Diff line change
Expand Up @@ -7,20 +7,22 @@ import chisel3.util._
import chisel3.util.experimental.forceName
import ee.hrzn.chryse.ChryseModule
import ee.hrzn.chryse.chisel.DirectionOf
import ee.hrzn.chryse.platform.BoardPlatform
import ee.hrzn.chryse.platform.BoardResources
import ee.hrzn.chryse.platform.Platform
import ee.hrzn.chryse.platform.PlatformBoard
import ee.hrzn.chryse.platform.PlatformBoardResources
import ee.hrzn.chryse.platform.resource

import java.lang.reflect.Modifier
import scala.collection.mutable

class ICE40Top[Top <: Module](
platform: BoardPlatform[_ <: BoardResources],
platform: PlatformBoard[_ <: PlatformBoardResources],
genTop: => Top,
) extends ChryseModule {
var lastPCF: Option[PCF] = None

// TODO (iCE40): SB_GBs between a lot more things.

private val clki = Wire(Clock())

private val clk_gb = Module(new SB_GB)
Expand Down
Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
package ee.hrzn.chryse.platform.ice40

import chisel3._
import ee.hrzn.chryse.platform.BoardPlatform
import ee.hrzn.chryse.platform.BoardResources
import ee.hrzn.chryse.platform.Platform
import ee.hrzn.chryse.platform.PlatformBoard
import ee.hrzn.chryse.platform.PlatformBoardResources
import ee.hrzn.chryse.platform.resource
import ee.hrzn.chryse.platform.resource.Pin._

final case class IceBreakerPlatform(ubtnReset: Boolean = false)
extends BoardPlatform[IceBreakerResources] {
extends PlatformBoard[IceBreakerResources] {
val id = "icebreaker"
val clockHz = 12_000_000

Expand All @@ -25,7 +25,8 @@ final case class IceBreakerPlatform(ubtnReset: Boolean = false)
}
}

class IceBreakerResources extends BoardResources {
class IceBreakerResources extends PlatformBoardResources {
// TODO: IO_STANDARD=SB_LVCMOS needs to be set on most.
val clock = resource.ClockSource(12_000_000).onPin(35)

val ubtn = resource.Button().inverted.onPin(10)
Expand All @@ -35,6 +36,10 @@ class IceBreakerResources extends BoardResources {
val ledg = resource.LED().inverted.onPin(37)
val ledr = resource.LED().inverted.onPin(11)

var spiFlash = resource
.SPIFlash()
.onPins(csN = 16, clock = 15, copi = 14, cipo = 17, wpN = 12, holdN = 13)

// Ideally (per Amaranth) a user can refer to these connectors to make their
// own resources, instead of just getting pins out of them.
val pmod1a = resource.Connector(
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ package ee.hrzn.chryse.platform.resource

import chisel3._

class Button extends DataResource[Bool](Input(Bool())) {
class Button extends ResourceData[Bool](Input(Bool())) {
private var invert = false // TODO: invert possibly belongs in a higher class

def inverted: this.type = {
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ package ee.hrzn.chryse.platform.resource

import chisel3._

case class ClockSource(hz: Int) extends DataResource[Clock](Input(Clock())) {}
case class ClockSource(hz: Int) extends ResourceData[Clock](Input(Clock())) {}

object ClockSource {
def apply(hz: Int) = new ClockSource(hz)
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,10 @@ package ee.hrzn.chryse.platform.resource

import chisel3._

class Connector[Ix, E <: SinglePinResource](
class Connector[Ix, E <: ResourceSinglePin](
gen: => E,
private val ixToPin: (Ix, Pin)*,
) extends Base {
) extends ResourceBase {
private val mappings: Map[Ix, E] = ixToPin
.map { case (i, p) =>
i -> gen.onPin(p)
Expand All @@ -17,11 +17,11 @@ class Connector[Ix, E <: SinglePinResource](
def setName(name: String): Unit =
mappings.foreach { case (i, e) => e.setName(s"$name$i") }

def data: Seq[DataResource[_ <: Data]] =
def data: Seq[ResourceData[_ <: Data]] =
mappings.flatMap(_._2.data).toSeq
}

object Connector {
def apply[Ix, E <: SinglePinResource](gen: => E, ixToPin: (Ix, Pin)*) =
def apply[Ix, E <: ResourceSinglePin](gen: => E, ixToPin: (Ix, Pin)*) =
new Connector(gen, ixToPin: _*)
}
8 changes: 4 additions & 4 deletions src/main/scala/ee/hrzn/chryse/platform/resource/InOut.scala
Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@ import chisel3._

// TODO: it's an error to use both "i" and "o" (tristate is a different kettle
// of fish entirely).
class InOut extends Base with SinglePinResource {
val i = new DataResource[Bool](Input(Bool())) {}
val o = new DataResource[Bool](Output(Bool())) {}
class InOut extends ResourceBase with ResourceSinglePin {
val i = new ResourceData[Bool](Input(Bool())) {}
val o = new ResourceData[Bool](Output(Bool())) {}

def setName(name: String): Unit = {
i.setName(s"$name")
Expand All @@ -19,7 +19,7 @@ class InOut extends Base with SinglePinResource {
this
}

def data: Seq[DataResource[_ <: Data]] = Seq(i, o)
def data: Seq[ResourceData[_ <: Data]] = Seq(i, o)
}

object InOut {
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/ee/hrzn/chryse/platform/resource/LED.scala
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ package ee.hrzn.chryse.platform.resource

import chisel3._

class LED extends DataResource[Bool](Output(Bool())) {
class LED extends ResourceData[Bool](Output(Bool())) {
private var invert = false // TODO: invert possibly belongs in a higher class

def inverted: this.type = {
Expand Down
Original file line number Diff line number Diff line change
@@ -1,24 +1,24 @@
package ee.hrzn.chryse.platform.resource

import chisel3._
import ee.hrzn.chryse.platform.BoardResources
import ee.hrzn.chryse.platform.PlatformBoardResources

import scala.collection.mutable.ArrayBuffer

trait Base {
trait ResourceBase {
def setName(name: String): Unit
def data: Seq[DataResource[_ <: Data]]
def data: Seq[ResourceData[_ <: Data]]
}

object Base {
def allFromBoardResources[T <: BoardResources](
object ResourceBase {
def allFromBoardResources[T <: PlatformBoardResources](
br: T,
): Seq[DataResource[_ <: Data]] = {
var out = ArrayBuffer[DataResource[_ <: Data]]()
): Seq[ResourceData[_ <: Data]] = {
var out = ArrayBuffer[ResourceData[_ <: Data]]()
for { f <- br.getClass().getDeclaredFields().iterator } {
f.setAccessible(true)
f.get(br) match {
case res: Base =>
case res: ResourceBase =>
out.appendAll(res.data)
case _ =>
}
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ package ee.hrzn.chryse.platform.resource

import chisel3._

abstract class DataResource[HW <: Data](gen: => HW) extends SinglePinResource {
abstract class ResourceData[HW <: Data](gen: => HW) extends ResourceSinglePin {
final private[chryse] var pinId: Option[Pin] = None
final var name: Option[String] = None

Expand Down Expand Up @@ -31,7 +31,7 @@ abstract class DataResource[HW <: Data](gen: => HW) extends SinglePinResource {
this
}

def data: Seq[DataResource[_ <: Data]] = Seq(this)
def data: Seq[ResourceData[_ <: Data]] = Seq(this)
}

case class InstSides[HW](user: HW, top: HW)
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
package ee.hrzn.chryse.platform.resource

trait SinglePinResource extends Base {
trait ResourceSinglePin extends ResourceBase {
def onPin(id: Pin): this.type
}
46 changes: 46 additions & 0 deletions src/main/scala/ee/hrzn/chryse/platform/resource/SPIFlash.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,46 @@
package ee.hrzn.chryse.platform.resource

import chisel3._

class SPIFlash extends ResourceBase {
// TODO NEXT: refactoring out inversion (and other interposed) logic here should be fruitful.
val cs = new ResourceData[Bool](Output(Bool())) {} // TODO: invert
val clock = new ResourceData[Clock](Output(Clock())) {} // XXX: Clock here OK?
val copi = new ResourceData[Bool](Output(Bool())) {}
val cipo = new ResourceData[Bool](Input(Bool())) {}
val wp = new ResourceData[Bool](Output(Bool())) {} // TODO: invert
val hold = new ResourceData[Bool](Output(Bool())) {} // TODO: invert

def setName(name: String): Unit = {
cs.setName(s"${name}_cs")
clock.setName(s"${name}_clock")
copi.setName(s"${name}_copi")
cipo.setName(s"${name}_cipo")
wp.setName(s"${name}_wp")
hold.setName(s"${name}_hold")
}

def onPins(
csN: Pin,
clock: Pin,
copi: Pin,
cipo: Pin,
wpN: Pin,
holdN: Pin,
): this.type = {
this.cs.onPin(csN)
this.clock.onPin(clock)
this.copi.onPin(copi)
this.cipo.onPin(cipo)
this.wp.onPin(wpN)
this.hold.onPin(holdN)
this
}

def data: Seq[ResourceData[_ <: Data]] =
Seq(cs, clock, copi, cipo, wp, hold)
}

object SPIFlash {
def apply() = new SPIFlash
}
10 changes: 6 additions & 4 deletions src/main/scala/ee/hrzn/chryse/platform/resource/UART.scala
Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,11 @@ package ee.hrzn.chryse.platform.resource

import chisel3._

class UART extends Base {
val rx = new DataResource[Bool](Input(Bool())) {}
val tx = new DataResource[Bool](Output(Bool())) {}
class UART extends ResourceBase {
// TODO (iCE40): lower IO_STANDARD=SB_LVTTL and PULLUP=1.
// TODO: these will differ per-platform so need to come in from outside.
val rx = new ResourceData[Bool](Input(Bool())) {}
val tx = new ResourceData[Bool](Output(Bool())) {}

def setName(name: String): Unit = {
rx.setName(s"${name}_rx")
Expand All @@ -17,7 +19,7 @@ class UART extends Base {
this
}

def data: Seq[DataResource[_ <: Data]] = Seq(rx, tx)
def data: Seq[ResourceData[_ <: Data]] = Seq(rx, tx)
}

object UART {
Expand Down
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