[CIR][CIRGen] Support for builtin __atomic_thread_fence
#1287
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I have just created the ODS definition at the moment to be sure if this is the way to go. |
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Initial step looks good, some inline comments. Note that this PR should come with CIRGen and LLVM lowering support, I suggest you first handle a very simple case of the fence and mark all paths not currently support with llvm_unrecheable("NYI"), so that you can go about working in incremental PRs to complete this.
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__atomic_thread_fence__atomic_thread_fence
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We just went over a rebase against upstream, apologies for the churn but please update your branch for this PR and force-push! |
Resolves llvm#1274 Implements atomic thread fence synchronization primitive corresponding to `atomic.thread_fence` CIR.
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| @@ -820,6 +821,16 @@ class CIRToLLVMAtomicFetchLowering | |||
| mlir::ConversionPatternRewriter &) const override; | |||
| }; | |||
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| // class CIRToLLVMAtomicFenceLowering | |||
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So far so good, time to add support for LLVM lowering as well, so we make sure the CIR operations contain all the info we need to lower to LLVM. You also need to add tests to this PR, see example in clang/test/CIR/CodeGen/abstract-cond.c.
| auto orderingAttr = | ||
| orderingVal.getDefiningOp()->getAttrOfType<mlir::IntegerAttr>("value"); | ||
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| cir::MemOrder ordering; |
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Probably no need for the switch: the order of the enum is already the value you are checking for, so just cast it directly:
// Memory order according to C++11 memory model
enum class MemOrder : uint32_t {
Relaxed = 0,
Consume = 1,
Acquire = 2,
Release = 3,
AcquireRelease = 4,
SequentiallyConsistent = 5,
};
Fix #1274
Implements atomic thread fence synchronization primitive corresponding to
atomic.thread_fenceCIR.