Properly initialize rings (SRAM is not 0'd out by default!) and add

some more checks
stm32-rs · Feb 4, 2023 · 2066f70 · 2066f70
1 parent 9b7dc07
commit 2066f70
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Showing 3 changed files with 44 additions and 37 deletions.
diff --git a/examples/arp.rs b/examples/arp.rs
@@ -33,17 +33,6 @@ const PHY_ADDR: u8 = 0;
 static TIME: Mutex<RefCell<usize>> = Mutex::new(RefCell::new(0));
 static ETH_PENDING: Mutex<RefCell<bool>> = Mutex::new(RefCell::new(false));
 
-/// On H7s, the ethernet DMA does not have access to the normal ram
-/// so we must explicitly put them in SRAM.
-#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
-static mut TX_DESCRIPTORS: [TxDescriptor; 4] = [TxDescriptor::new(); 4];
-#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
-static mut TX_BUFFERS: [[u8; MTU + 2]; 4] = [[0u8; MTU + 2]; 4];
-#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
-static mut RX_DESCRIPTORS: [RxDescriptor; 4] = [RxDescriptor::new(); 4];
-#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
-static mut RX_BUFFERS: [[u8; MTU + 2]; 4] = [[0u8; MTU + 2]; 4];
-
 #[entry]
 fn main() -> ! {
     let p = Peripherals::take().unwrap();
@@ -57,8 +46,7 @@ fn main() -> ! {
 
     let (eth_pins, mdio, mdc, _) = common::setup_pins(gpio);
 
-    let rx_ring = RxDescriptorRing::new(unsafe { &mut RX_DESCRIPTORS }, unsafe { &mut RX_BUFFERS });
-    let tx_ring = TxDescriptorRing::new(unsafe { &mut TX_DESCRIPTORS }, unsafe { &mut TX_BUFFERS });
+    let (tx_ring, rx_ring) = crate::common::setup_rings();
 
     let Parts {
         mut dma,

diff --git a/examples/common.rs b/examples/common.rs
@@ -4,7 +4,13 @@
 //!
 //! Note that this module isn't an example by itself.
 
-use stm32_eth::{hal::gpio::GpioExt, PartsIn};
+use core::mem::MaybeUninit;
+
+use stm32_eth::{
+    dma::{RxDescriptor, RxDescriptorRing, TxDescriptor, TxDescriptorRing},
+    hal::gpio::GpioExt,
+    PartsIn, MTU,
+};
 
 #[cfg(feature = "f-series")]
 use stm32_eth::hal::rcc::Clocks;
@@ -17,6 +23,31 @@ pub use pins::{setup_pins, Gpio};
 use fugit::RateExtU32;
 use stm32_eth::hal::rcc::RccExt;
 
+/// On H7s, the ethernet DMA does not have access to the normal ram
+/// so we must explicitly put them in SRAM.
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
+static mut TX_DESCRIPTORS: MaybeUninit<[TxDescriptor; 4]> = MaybeUninit::uninit();
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
+static mut TX_BUFFERS: MaybeUninit<[[u8; MTU + 2]; 4]> = MaybeUninit::uninit();
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
+static mut RX_DESCRIPTORS: MaybeUninit<[RxDescriptor; 4]> = MaybeUninit::uninit();
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
+static mut RX_BUFFERS: MaybeUninit<[[u8; MTU + 2]; 4]> = MaybeUninit::uninit();
+
+/// Set up the buffers to be used
+pub fn setup_rings() -> (TxDescriptorRing<'static>, RxDescriptorRing<'static>) {
+    let tx_desc = unsafe { TX_DESCRIPTORS.write([TxDescriptor::new(); 4]) };
+    let tx_buf = unsafe { TX_BUFFERS.write([[0u8; MTU + 2]; 4]) };
+
+    let rx_desc = unsafe { RX_DESCRIPTORS.write([RxDescriptor::new(); 4]) };
+    let rx_buf = unsafe { RX_BUFFERS.write([[0u8; MTU + 2]; 4]) };
+
+    (
+        TxDescriptorRing::new(tx_desc, tx_buf),
+        RxDescriptorRing::new(rx_desc, rx_buf),
+    )
+}
+
 /// Setup the clocks and return clocks and a GPIO struct that
 /// can be used to set up all of the pins.
 ///

diff --git a/examples/rtic-timestamp.rs b/examples/rtic-timestamp.rs
@@ -65,27 +65,13 @@ mod app {
     #[monotonic(binds = SysTick, default = true)]
     type Monotonic = Systick<1000>;
 
-    /// On H7s, the ethernet DMA does not have access to the normal ram
-    /// so we must explicitly put them in SRAM.
-    #[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
-    static mut TX_DESCRIPTORS: [TxDescriptor; 4] = [TxDescriptor::new(); 4];
-    #[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
-    static mut TX_BUFFERS: [[u8; MTU + 2]; 4] = [[0u8; MTU + 2]; 4];
-    #[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
-    static mut RX_DESCRIPTORS: [RxDescriptor; 4] = [RxDescriptor::new(); 4];
-    #[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
-    static mut RX_BUFFERS: [[u8; MTU + 2]; 4] = [[0u8; MTU + 2]; 4];
-
     #[init]
     fn init(cx: init::Context) -> (Shared, Local, init::Monotonics) {
         defmt::info!("Pre-init");
         let core = cx.core;
         let p = cx.device;
 
-        let rx_ring =
-            RxDescriptorRing::new(unsafe { &mut RX_DESCRIPTORS }, unsafe { &mut RX_BUFFERS });
-        let tx_ring =
-            TxDescriptorRing::new(unsafe { &mut TX_DESCRIPTORS }, unsafe { &mut TX_BUFFERS });
+        let (tx_ring, rx_ring) = crate::common::setup_rings();
 
         let (clocks, gpio, ethernet) = crate::common::setup_peripherals(p);
         let mono = Systick::new(core.SYST, clocks.hclk().raw());
@@ -192,7 +178,7 @@ mod app {
                 buf[12..14].copy_from_slice(&ETH_TYPE);
                 buf[14..22].copy_from_slice(&now.raw().to_be_bytes());
             })
-            .ok();
+            .unwrap();
             *tx_id = Some((tx_id_val, now));
             *tx_id_ctr += 1;
             *tx_id_ctr |= 0x8000_0000;
@@ -210,7 +196,7 @@ mod app {
             cx.shared.scheduled_time,
         )
             .lock(|dma, tx_id, ptp, _sched_time| {
-                dma.interrupt_handler();
+                let interrupt_summary = dma.interrupt_handler();
 
                 #[cfg(not(feature = "stm32f107"))]
                 {
@@ -302,15 +288,17 @@ mod app {
                     }
                 }
 
-                if let Some((tx_id, sent_time)) = tx_id.take() {
-                    if let Ok(ts) = dma.get_timestamp_for_id(PacketId(tx_id)) {
-                        defmt::info!("TX timestamp: {}", ts);
-                        defmt::debug!(
+                if interrupt_summary.is_tx {
+                    if let Some((tx_id, sent_time)) = tx_id.take() {
+                        if let Ok(ts) = dma.get_timestamp_for_id(PacketId(tx_id)) {
+                            defmt::info!("TX timestamp: {}", ts);
+                            defmt::debug!(
                         "Diff between TX timestamp and the time that was put into the packet: {}",
                         ts - sent_time
                     );
-                    } else {
-                        defmt::warn!("Failed to retrieve TX timestamp");
+                        } else {
+                            defmt::warn!("Failed to retrieve TX timestamp");
+                        }
                     }
                 }
             });