Preparing to release v0.6.0 (#539)

intel · Dec 31, 2024 · 121951b · 121951b
1 parent 8cd55f0
commit 121951b
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Showing 5 changed files with 7 additions and 5 deletions.
diff --git a/.gitignore b/.gitignore
@@ -17,8 +17,9 @@ tmp_test/
 *.vcd
 *_fsm.md
 .vscode/*
-devtools_options.yaml
+./devtools_options.yaml
 
 # Exceptions
 !.vscode/extensions.json
 !test/example_icarus_waves.vcd
+!test/sv_param_passthrough.sv
diff --git a/.pubignore b/.pubignore
@@ -17,11 +17,12 @@ tmp_test/
 *.vcd
 *_fsm.md
 .vscode/*
-devtools_options.yaml
+./devtools_options.yaml
 
 # Exceptions
 !.vscode/extensions.json
 !test/example_icarus_waves.vcd
+!test/sv_param_passthrough.sv
 
 # Release with devtools build
 !extension/devtools/build
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,4 +1,4 @@
-## Next release
+## 0.6.0
 
 - Added `LogicNet`, `inOut`s, and `TriStateBuffer` to enable multi-directional wires, ports, and drivers. Includes support for "wire-only" operations supporting multiple drivers.
 - Deprecated `CustomSystemVerilog` in favor of `SystemVerilog`, which has similar functionality but supports `inOut` ports, and collapses all ports into a single `ports` argument, as well as some other new features like custom definitions and parameter passthroughs.

diff --git a/lib/src/utilities/config.dart b/lib/src/utilities/config.dart
@@ -10,5 +10,5 @@
 /// A utility for ROHD configuration file.
 class Config {
   /// The version of the ROHD framework.
-  static const String version = '0.5.3';
+  static const String version = '0.6.0';
 }
diff --git a/pubspec.yaml b/pubspec.yaml
@@ -1,5 +1,5 @@
 name: rohd
-version: 0.5.3
+version: 0.6.0
 description: The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware.
 homepage: https://intel.github.io/rohd-website
 repository: https://github.com/intel/rohd