Fix bug where non-async flop generates async flop (#564)

.github/workflows/general.yml

@@ -19,7 +19,7 @@ jobs:
     runs-on: ${{ github.repository_owner == 'intel' && 'intel-ubuntu-latest' || 'ubuntu-latest' }}
     steps:
       - name: Checkout
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
 
       - name: Lint Markdown files
         uses: DavidAnson/markdownlint-cli2-action@v11
@@ -34,6 +34,8 @@ jobs:
 
       - name: Setup Dart
         uses: dart-lang/setup-dart@v1
+        with:
+          sdk: 3.6.2 # downgrade pending https://github.com/dart-lang/dartdoc/issues/3996
 
       - name: Setup Node
         uses: actions/setup-node@v4
@@ -81,6 +83,8 @@ jobs:
 
       - name: Setup Dart
         uses: dart-lang/setup-dart@v1
+        with:
+          sdk: 3.6.2 # downgrade pending https://github.com/dart-lang/dartdoc/issues/3996
 
       - name: Install project dependencies
         run: tool/gh_actions/install_dependencies.sh

analysis_options.yaml

@@ -122,7 +122,6 @@ linter:
     - one_member_abstracts
     - only_throw_errors
     - overridden_fields
-    - package_api_docs
     - package_names
     - package_prefixed_library_names
     - parameter_assignments
@@ -211,7 +210,6 @@ linter:
     - unnecessary_to_list_in_spreads
     # - unreachable_from_main
     - unrelated_type_equality_checks
-    - unsafe_html
     - use_build_context_synchronously
     - use_colored_box
     - use_decorated_box

lib/src/modules/conditionals/flop.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2024 Intel Corporation
+// Copyright (C) 2021-2025 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // flop.dart
@@ -184,7 +184,7 @@ class FlipFlop extends Module with SystemVerilog {
 
     final triggerString = [
       clk,
-      if (reset != null) reset,
+      if (reset != null && asyncReset) reset,
     ].map((e) => 'posedge $e').join(' or ');
 
     final svBuffer = StringBuffer('always_ff @($triggerString) ');

lib/src/signals/wire_net.dart

@@ -214,6 +214,9 @@ class _WireNetBlasted extends _Wire implements _WireNet {
   @override
   LogicValue get value => LogicValue.ofIterable(_wires.map((e) => e.value));
 
+  @override
+  LogicValue get _currentValue => throw UnsupportedError('Unnecessary');
+
   @override
   set _currentValue(LogicValue newValue) =>
       // this is delegated away via calling `value` getter

test/async_reset_test.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2024 Intel Corporation
+// Copyright (C) 2024-2025 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // async_reset_test.dart
@@ -74,14 +74,14 @@ class MultipleTriggerSeq extends Module {
   }
 }
 
-class AsyncResetMod extends Module {
+class ResetMod extends Module {
   Logic get val => output('val');
-  AsyncResetMod({
-    required Logic clk,
+  ResetMod({
+    required Logic? clk,
     required Logic reset,
     required void Function(Logic clk, Logic reset, Logic val) seqBuilder,
   }) {
-    clk = addInput('clk', clk);
+    clk = clk == null ? SimpleClockGenerator(10).clk : addInput('clk', clk);
     reset = addInput('reset', reset);
     addOutput('val');
 
@@ -94,6 +94,89 @@ void main() {
     await Simulator.reset();
   });
 
+  group('non-async reset samples non-async-ly', () {
+    final seqMechanism = {
+      'Sequential.multi no asyncReset': (Logic clk, Logic reset, Logic val) =>
+          Sequential.multi(
+            [clk],
+            reset: reset,
+            [
+              val < 1,
+            ],
+          ),
+      'Sequential with no asyncReset': (Logic clk, Logic reset, Logic val) =>
+          Sequential(
+            clk,
+            reset: reset,
+            [
+              val < 1,
+            ],
+          ),
+      'FlipFlop with no asyncReset': (Logic clk, Logic reset, Logic val) {
+        val <=
+            FlipFlop(
+              clk,
+              reset: reset,
+              Const(1),
+            ).q;
+      },
+      'flop with no asyncReset': (Logic clk, Logic reset, Logic val) {
+        val <=
+            flop(
+              clk,
+              reset: reset,
+              Const(1),
+            );
+      },
+    };
+
+    for (final mechanism in seqMechanism.entries) {
+      group('using ${mechanism.key}', () {
+        test('simcompare no clk sync reset', () async {
+          final mod = ResetMod(
+            clk: Logic(name: 'clk'),
+            reset: Logic(name: 'reset'),
+            seqBuilder: mechanism.value,
+          );
+
+          await mod.build();
+
+          final vectors = [
+            Vector({'clk': 0, 'reset': 0}, {}),
+            Vector({'clk': 1, 'reset': 0}, {'val': 1}),
+            Vector({'clk': 1, 'reset': 0}, {'val': 1}),
+            Vector({'clk': 1, 'reset': 1}, {'val': 1}),
+            Vector({'clk': 1, 'reset': 1}, {'val': 1}),
+          ];
+
+          await SimCompare.checkFunctionalVector(mod, vectors);
+          SimCompare.checkIverilogVector(mod, vectors);
+        });
+
+        test('simcompare with clk sync reset', () async {
+          final mod = ResetMod(
+            clk: null,
+            reset: Logic(name: 'reset'),
+            seqBuilder: mechanism.value,
+          );
+
+          await mod.build();
+
+          final vectors = [
+            Vector({'reset': 0}, {}),
+            Vector({'reset': 0}, {'val': 1}),
+            Vector({'reset': 0}, {'val': 1}),
+            Vector({'reset': 1}, {'val': 1}),
+            Vector({'reset': 1}, {'val': 0}),
+          ];
+
+          await SimCompare.checkFunctionalVector(mod, vectors);
+          SimCompare.checkIverilogVector(mod, vectors);
+        });
+      });
+    }
+  });
+
   group('async reset samples correct reset value', () {
     final seqMechanism = {
       'Sequential.multi': (Logic clk, Logic reset, Logic val) =>
@@ -165,7 +248,7 @@ void main() {
         });
 
         test('simcompare', () async {
-          final mod = AsyncResetMod(
+          final mod = ResetMod(
             clk: Logic(name: 'clk'),
             reset: Logic(name: 'reset'),
             seqBuilder: mechanism.value,