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Add VhdlParameterType class to support vector and array parameter types #18

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Add VhdlParameterType class to support vector and array parameter types #18

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Commits on Jul 11, 2019

  1. Add entity parsing

    @andresmanelli
    andresmanelli committed Jul 11, 2019
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  2. Add default values for ports and generics

    @andresmanelli
    andresmanelli committed Jul 11, 2019
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Commits on Jan 10, 2020

  1. Add line comments to port definitions

    Katharina Ceesay-Seitz committed Jan 10, 2020
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  2. Destinguish between line comments for ports of the same type and for … 

    …the whole port list
    Katharina Ceesay-Seitz committed Jan 10, 2020
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  3. Make it Python3 friendly

    Katharina Ceesay-Seitz committed Jan 10, 2020
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  4. Add comment for param_desc attribute of class VhdlParameter

    Katharina Ceesay-Seitz committed Jan 10, 2020
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Commits on Jul 28, 2020

  1. Add VhdlParameterType class to support vector and array parameter types

    Katharina Ceesay-Seitz committed Jul 28, 2020
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Commits on Dec 7, 2020

  1. Support end entity with entity keyword and name

    Katharina Ceesay-Seitz committed Dec 7, 2020
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  2. Merge branch 'portLineComments' into VhdlParameterType

    Katharina Ceesay-Seitz committed Dec 7, 2020
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  3. Improve pattern for array_range_val

    Katharina Ceesay-Seitz committed Dec 7, 2020
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Commits on Dec 9, 2020

  1. Merge pull request andresmanelli#4 from andresmanelli/entity 

     Add entity parsing
    @andresmanelli
    andresmanelli authored Dec 9, 2020
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Commits on Dec 10, 2020

  1. Add line comments to port definitions

    Katharina Ceesay-Seitz committed Dec 10, 2020
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  2. Destinguish between line comments for ports of the same type and for … 

    …the whole port list
    Katharina Ceesay-Seitz committed Dec 10, 2020
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  3. Make it Python3 friendly

    Katharina Ceesay-Seitz committed Dec 10, 2020
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  4. Add comment for param_desc attribute of class VhdlParameter

    Katharina Ceesay-Seitz committed Dec 10, 2020
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  5. Support end entity with entity keyword and name

    Katharina Ceesay-Seitz committed Dec 10, 2020
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Commits on May 27, 2021

  1. Add VhdlParameterType class to support vector and array parameter types

    Katharina Ceesay-Seitz committed May 27, 2021
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  2. Improve pattern for array_range_val

    Katharina Ceesay-Seitz committed May 27, 2021
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  3. Rename bound vars for array parameter types. Update regex

    Katharina Ceesay-Seitz committed May 27, 2021
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  4. Store array bounds

    Katharina Ceesay-Seitz committed May 27, 2021
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  5. Merge branch 'VhdlParameterType' of https://github.com/KatCe/hdlparse … 

    …into VhdlParameterType

Conflicts:
	hdlparse/vhdl_parser.py
    Katharina Ceesay-Seitz committed May 27, 2021
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  6. Merge pull request andresmanelli#2 from KatCe/portLineComments 

    Store port line comments
    @andresmanelli
    andresmanelli authored May 27, 2021
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Commits on Aug 7, 2021

  1. Add line comments to port definitions

    Katharina Ceesay-Seitz committed Aug 7, 2021
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  2. Destinguish between line comments for ports of the same type and for … 

    …the whole port list
    Katharina Ceesay-Seitz committed Aug 7, 2021
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  3. Add VhdlParameterType class to support vector and array parameter types

    Katharina Ceesay-Seitz committed Aug 7, 2021
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  4. Improve pattern for array_range_val

    Katharina Ceesay-Seitz committed Aug 7, 2021
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  5. Rename bound vars for array parameter types. Update regex

    Katharina Ceesay-Seitz committed Aug 7, 2021
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  6. Store array bounds

    Katharina Ceesay-Seitz committed Aug 7, 2021
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  7. Merge branch 'master' of https://github.com/KatCe/hdlparse

    Katharina Ceesay-Seitz committed Aug 7, 2021
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