Skip to content

Actions: apparentlymart/unicorn

Actions

PyPI 📦 Distribution

Actions

Loading...
Loading

Show workflow options

Create status badge

Loading
PyPI-publishing.yml
22 workflow runs
22 workflow runs

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

wip fixing portability problems PyPI 📦 Distribution #22: Commit ed0d87c pushed by apparentlymart
November 11, 2024 00:13 7m 59s f-riscv-priv-reg
f-riscv-priv-reg
November 11, 2024 00:13 7m 59s
riscv: Expose privilege level as pseudo-register PRIV PyPI 📦 Distribution #21: Commit 8aa4162 pushed by apparentlymart
September 30, 2024 00:33 8m 1s matkins-unmerged-prs
matkins-unmerged-prs
September 30, 2024 00:33 8m 1s
riscv: Invalid 32-bit instruction should not decrement pc PyPI 📦 Distribution #20: Commit 02c9ead pushed by apparentlymart
September 9, 2024 23:08 5m 34s matkins-unmerged-prs
matkins-unmerged-prs
September 9, 2024 23:08 5m 34s
target/riscv: fix wfi exception behavior PyPI 📦 Distribution #19: Commit 3689586 pushed by apparentlymart
September 3, 2024 21:05 8m 17s matkins-unmerged-prs
matkins-unmerged-prs
September 3, 2024 21:05 8m 17s
target/riscv: fix wfi exception behavior PyPI 📦 Distribution #18: Commit 58f1a61 pushed by apparentlymart
September 3, 2024 20:45 6m 40s f-qemu-backport-wfi-umode
f-qemu-backport-wfi-umode
September 3, 2024 20:45 6m 40s
riscv: Invalid 32-bit instruction should not decrement pc PyPI 📦 Distribution #17: Commit 9b75f8c pushed by apparentlymart
August 28, 2024 22:28 5m 33s matkins-unmerged-prs
matkins-unmerged-prs
August 28, 2024 22:28 5m 33s
riscv: Invalid 32-bit instruction should not decrement pc PyPI 📦 Distribution #16: Commit ac1b374 pushed by apparentlymart
August 28, 2024 21:06 5m 46s b-riscv-invalidinsn-pcadj
b-riscv-invalidinsn-pcadj
August 28, 2024 21:06 5m 46s
riscv: Expose privilege level as pseudo-register PRIV PyPI 📦 Distribution #15: Commit b389239 pushed by apparentlymart
August 27, 2024 15:45 11m 1s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:45 11m 1s
riscv: Expose privilege level as pseudo-register PRIV PyPI 📦 Distribution #14: Commit e5a0a35 pushed by apparentlymart
August 27, 2024 15:38 15m 2s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:38 15m 2s
riscv: Expose privilege level as pseudo-register PRIV PyPI 📦 Distribution #13: Commit a7cf173 pushed by apparentlymart
August 27, 2024 15:35 13m 36s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:35 13m 36s
riscv: Expose privilege level as pseudo-register PRIV PyPI 📦 Distribution #12: Commit 50f1f15 pushed by apparentlymart
August 27, 2024 15:34 5m 25s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:34 5m 25s
riscv: Expose privilege level as pseudo-register PRIV PyPI 📦 Distribution #11: Commit eee98f0 pushed by apparentlymart
August 27, 2024 15:24 6m 4s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:24 6m 4s
riscv: Expose privilege level as pseudo-register PRIV PyPI 📦 Distribution #10: Commit 6025238 pushed by apparentlymart
August 27, 2024 15:19 6m 17s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:19 6m 17s
riscv: Expose privilege level as pseudo-register PRIV PyPI 📦 Distribution #9: Commit f30c808 pushed by apparentlymart
August 27, 2024 15:16 6m 20s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:16 6m 20s
riscv: Expose privilege level as pseudo-register PRIV PyPI 📦 Distribution #8: Commit 33ecfe5 pushed by apparentlymart
August 27, 2024 14:42 6m 26s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 14:42 6m 26s
riscv: Expose privilege level as pseudo-register PRIV PyPI 📦 Distribution #7: Commit c861627 pushed by apparentlymart
August 27, 2024 01:50 5m 40s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 01:50 5m 40s
rust-tests: Don't use virtual TLB mode in the memory error tests PyPI 📦 Distribution #6: Commit 507494a pushed by apparentlymart
August 26, 2024 17:15 6m 8s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 17:15 6m 8s
rust-tests: handling of RISC-V memory access errors PyPI 📦 Distribution #5: Commit 761b0c9 pushed by apparentlymart
August 26, 2024 16:05 11m 0s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 16:05 11m 0s
rust-tests: handling of RISC-V memory access errors PyPI 📦 Distribution #4: Commit 62d7dc2 pushed by apparentlymart
August 26, 2024 02:22 5m 52s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 02:22 5m 52s
rust-tests: Some RISC-V emulation tests PyPI 📦 Distribution #3: Commit 5329930 pushed by apparentlymart
August 26, 2024 01:29 5m 44s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 01:29 5m 44s
rust-tests: Some RISC-V emulation tests PyPI 📦 Distribution #2: Commit e97dd68 pushed by apparentlymart
August 26, 2024 01:13 5m 46s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 01:13 5m 46s
rust-tests: Some RISC-V emulation tests PyPI 📦 Distribution #1: Commit 27eb923 pushed by apparentlymart
August 26, 2024 01:10 5m 41s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 01:10 5m 41s