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riscv: Expose privilege level as pseudo-register PRIV Zig Build #23: Commit 90bdb39 pushed by apparentlymart
November 11, 2024 00:26 7m 46s f-riscv-priv-reg
f-riscv-priv-reg
November 11, 2024 00:26 7m 46s
wip fixing portability problems Zig Build #22: Commit ed0d87c pushed by apparentlymart
November 11, 2024 00:13 5m 46s f-riscv-priv-reg
f-riscv-priv-reg
November 11, 2024 00:13 5m 46s
riscv: Expose privilege level as pseudo-register PRIV Zig Build #21: Commit 8aa4162 pushed by apparentlymart
September 30, 2024 00:33 4m 54s matkins-unmerged-prs
matkins-unmerged-prs
September 30, 2024 00:33 4m 54s
riscv: Invalid 32-bit instruction should not decrement pc Zig Build #20: Commit 02c9ead pushed by apparentlymart
September 9, 2024 23:08 10m 25s matkins-unmerged-prs
matkins-unmerged-prs
September 9, 2024 23:08 10m 25s
target/riscv: fix wfi exception behavior Zig Build #19: Commit 3689586 pushed by apparentlymart
September 3, 2024 21:05 10m 33s matkins-unmerged-prs
matkins-unmerged-prs
September 3, 2024 21:05 10m 33s
target/riscv: fix wfi exception behavior Zig Build #18: Commit 58f1a61 pushed by apparentlymart
September 3, 2024 20:45 13m 17s f-qemu-backport-wfi-umode
f-qemu-backport-wfi-umode
September 3, 2024 20:45 13m 17s
riscv: Invalid 32-bit instruction should not decrement pc Zig Build #17: Commit 9b75f8c pushed by apparentlymart
August 28, 2024 22:28 15m 32s matkins-unmerged-prs
matkins-unmerged-prs
August 28, 2024 22:28 15m 32s
riscv: Invalid 32-bit instruction should not decrement pc Zig Build #16: Commit ac1b374 pushed by apparentlymart
August 28, 2024 21:06 18m 34s b-riscv-invalidinsn-pcadj
b-riscv-invalidinsn-pcadj
August 28, 2024 21:06 18m 34s
riscv: Expose privilege level as pseudo-register PRIV Zig Build #15: Commit b389239 pushed by apparentlymart
August 27, 2024 15:45 16m 43s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:45 16m 43s
riscv: Expose privilege level as pseudo-register PRIV Zig Build #14: Commit e5a0a35 pushed by apparentlymart
August 27, 2024 15:38 13m 40s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:38 13m 40s
riscv: Expose privilege level as pseudo-register PRIV Zig Build #13: Commit a7cf173 pushed by apparentlymart
August 27, 2024 15:35 15m 48s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:35 15m 48s
riscv: Expose privilege level as pseudo-register PRIV Zig Build #12: Commit 50f1f15 pushed by apparentlymart
August 27, 2024 15:34 10m 42s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:34 10m 42s
riscv: Expose privilege level as pseudo-register PRIV Zig Build #11: Commit eee98f0 pushed by apparentlymart
August 27, 2024 15:24 15m 15s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:24 15m 15s
riscv: Expose privilege level as pseudo-register PRIV Zig Build #10: Commit 6025238 pushed by apparentlymart
August 27, 2024 15:19 12m 7s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:19 12m 7s
riscv: Expose privilege level as pseudo-register PRIV Zig Build #9: Commit f30c808 pushed by apparentlymart
August 27, 2024 15:16 11m 38s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 15:16 11m 38s
riscv: Expose privilege level as pseudo-register PRIV Zig Build #8: Commit 33ecfe5 pushed by apparentlymart
August 27, 2024 14:42 9m 30s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 14:42 9m 30s
riscv: Expose privilege level as pseudo-register PRIV Zig Build #7: Commit c861627 pushed by apparentlymart
August 27, 2024 01:50 12m 30s f-riscv-priv-reg
f-riscv-priv-reg
August 27, 2024 01:50 12m 30s
rust-tests: Don't use virtual TLB mode in the memory error tests Zig Build #6: Commit 507494a pushed by apparentlymart
August 26, 2024 17:15 15m 8s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 17:15 15m 8s
rust-tests: handling of RISC-V memory access errors Zig Build #5: Commit 761b0c9 pushed by apparentlymart
August 26, 2024 16:05 18m 8s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 16:05 18m 8s
rust-tests: handling of RISC-V memory access errors Zig Build #4: Commit 62d7dc2 pushed by apparentlymart
August 26, 2024 02:22 11m 59s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 02:22 11m 59s
rust-tests: Some RISC-V emulation tests Zig Build #3: Commit 5329930 pushed by apparentlymart
August 26, 2024 01:29 12m 28s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 01:29 12m 28s
rust-tests: Some RISC-V emulation tests Zig Build #2: Commit e97dd68 pushed by apparentlymart
August 26, 2024 01:13 12m 52s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 01:13 12m 52s
rust-tests: Some RISC-V emulation tests Zig Build #1: Commit 27eb923 pushed by apparentlymart
August 26, 2024 01:10 15m 14s b-riscv-exc-interrupt
b-riscv-exc-interrupt
August 26, 2024 01:10 15m 14s